Work place: Department of ECE,K.L.N College of Information Technology,Madurai , India
Research Interests: Image Processing
Karunakaran.P is currently working as Assistant Professor in the Department of ECE, K.L.N College of Information Technology, Madurai India. He has completed his Bachelor Degree in Electronics and Communication (2006), Masters in VLSI Design (2010).He had published few journals and attended many Conferences in National and International Level. His research areas are VLSI Testing, low Power Testing and Image processing
DOI: https://doi.org/10.5815/ijieeb.2012.04.07, Pub. Date: 8 Aug. 2012
Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.[...] Read more.
DOI: https://doi.org/10.5815/ijitcs.2012.09.09, Pub. Date: 8 Aug. 2012
Many distributed applications require a group of destinations to be coordinated to a single source. Multicasting is a communication paradigm to implement these distributed applications. In multicasting, at least one of the member in the group cannot satisfy the service requirement of the application, the multicast request said to be blocked. On the contrary in manycasting, destinations can join or leave the group, depending upon whether it satisfies the service requirement or not. Manycasting is performed over optical burst-switched (OBS) networks based on multiple qualities of service (QoS) constraints. The multiple constraints can be in the form of physical layer impairments, transmission delay, and reliability of the link. Destinations qualify only if they satisfy the Qos constraints. We develop a simple yet efficient routing algorithm which is based on the classic shortest path algorithm. The proposed layer aware FEC (L-FEC) generates repair symbols so that protection of less important dependency layers can be used with protection of more important layers for combined error correction.[...] Read more.
DOI: https://doi.org/10.5815/ijigsp.2012.07.07, Pub. Date: 28 Jul. 2012
A fast filtering algorithm for color video based on Neighborhood Correlation Filtering is presented. By utilizing a 3 × 3 pixel template, the algorithm can discriminate and filter various patterns of noise spots or blocks. In contrast with many kinds of median filtering algorithm, which may cause image blurring, it has much higher edge preserving ability. Furthermore, this algorithm is able to synchronously reflect image quality via amount, location and density statistics. Filtering of detected pixels is done by NCF algorithm based on a noise adaptive mean absolute difference. The experiments show that the proposed method outperforms other state-of-the-art filters both visually and in terms of objective quality measures such as the mean absolute error (MAE), the peak-signal-to-noise ratio (PSNR) and the normalized color difference (NCD).[...] Read more.
DOI: https://doi.org/10.5815/ijisa.2012.06.05, Pub. Date: 8 Jun. 2012
In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.[...] Read more.
DOI: https://doi.org/10.5815/ijigsp.2012.03.07, Pub. Date: 8 Apr. 2012
Edge detection of an image reduces significantly the amount of data and filters out information that may be regarded as less irrelevant. Edge detection is efficient in medical imaging. Pulse mode neural networks are becoming an attractive solution for function approximation based on frequency modulation. Early pulse mode implementation suffers from some network constraints due to weight range limitations. To provide the best edge detection, the basic algorithm is modified to have pulse mode operations for effective hardware implementation. In this project a new pulse mode network architecture using floating point operations is used in the activation function. By using floating point number system for synapse weight value representation, any function can be approximated by the network. The proposed pulse mode MNN is used to detect the edges in images forming a heterogeneous data base. It shows good learning capability. In addition, four edge detection techniques have been compared. The coding is written in verilog and the final result have been simulated using Xilinx ISE simulator.[...] Read more.
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