Work place: Department of ECE, Sudharsan college Engineering, Trichy, India

E-mail: kapilachander84@gmail.com


Research Interests: Physics, Physics & Mathematics, Computational Physics


Kapilachander.T is currently working Assistant Professor, Department of ECE, Sudharsan Engineering College, Trichy, India.He has completed his Bachelor Degree in Electronics and Communication (2006), Masters in VLSI Design (2008) He worked for various institution in electronics and communication department around many states in India .He has published many journals and attended many Conferences in National and International Level. His research areas are VLSI Physical Design ,Testing, Low Power, and CAD Algorithms.

Author Articles
Denoising of Noisy Pixels in Video by Neighborhood Correlation Filtering Algorithm

By P.Karunakaran S.Venkatraman Hameem Shanavas .I T.Kapilachander

DOI: https://doi.org/10.5815/ijigsp.2012.07.07, Pub. Date: 28 Jul. 2012

A fast filtering algorithm for color video based on Neighborhood Correlation Filtering is presented. By utilizing a 3 × 3 pixel template, the algorithm can discriminate and filter various patterns of noise spots or blocks. In contrast with many kinds of median filtering algorithm, which may cause image blurring, it has much higher edge preserving ability. Furthermore, this algorithm is able to synchronously reflect image quality via amount, location and density statistics. Filtering of detected pixels is done by NCF algorithm based on a noise adaptive mean absolute difference. The experiments show that the proposed method outperforms other state-of-the-art filters both visually and in terms of objective quality measures such as the mean absolute error (MAE), the peak-signal-to-noise ratio (PSNR) and the normalized color difference (NCD).

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Power Optimized Multiplier Using Shannon Based Multiplexing Logic

By P.Karunakaran S.Venkatraman I.Hameem Shanavas T.Kapilachander

DOI: https://doi.org/10.5815/ijisa.2012.06.05, Pub. Date: 8 Jun. 2012

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.

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Edge Detection System using Pulse Mode Neural Network for Image Enhancement

By S.Jagadeesh Babu P.Karunakaran S.Venkatraman Hameem Shanavas .I T.Kapilachander

DOI: https://doi.org/10.5815/ijigsp.2012.03.07, Pub. Date: 8 Apr. 2012

Edge detection of an image reduces significantly the amount of data and filters out information that may be regarded as less irrelevant. Edge detection is efficient in medical imaging. Pulse mode neural networks are becoming an attractive solution for function approximation based on frequency modulation. Early pulse mode implementation suffers from some network constraints due to weight range limitations. To provide the best edge detection, the basic algorithm is modified to have pulse mode operations for effective hardware implementation. In this project a new pulse mode network architecture using floating point operations is used in the activation function. By using floating point number system for synapse weight value representation, any function can be approximated by the network. The proposed pulse mode MNN is used to detect the edges in images forming a heterogeneous data base. It shows good learning capability. In addition, four edge detection techniques have been compared. The coding is written in verilog and the final result have been simulated using Xilinx ISE simulator.

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Technical Study on Low Power VLSI methods

By T.Kapilachander I.Hameem Shanavas V.Venkataraman

DOI: https://doi.org/10.5815/ijieeb.2012.01.08, Pub. Date: 8 Feb. 2012

In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are briefly discussed in this paper. Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate. Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. For a Integrated Circuit (IC) perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII. This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip

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