Work place: Department of Electronics & Communication, VEL TECH, Avadi

E-mail: dinesh84@gmail.com


Research Interests:


T.R.DineshKumar is currently working Assistant Professor, Department of ECE, Vel Tech, Avadi, Chennai 

Author Articles
Design Of High Performance Reconfigurable Routers Using Fpga

By R.Parthasarathi P.Karunakaran S.Venkatraman T.R.DineshKumar I.Hameem Shanavas

DOI: https://doi.org/10.5815/ijieeb.2012.04.07, Pub. Date: 8 Aug. 2012

Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.

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