Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

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Maede Kaviani 1 Hojjat Sharifi 2,* Mahdi Dolatshahi 1 Keivan Navi 3

1. Islamic Azad University, Najafabad, Esfahan PO BOX: 8514143131, Iran

2. Vali-e-Asr University of Rafsanjan, Rafsanjan PO BOX: 518, Iran

3. Shahid Beheshti University, GC, Tehran PO BOX: 1983963113, Iran

* Corresponding author.


Received: 23 Sep. 2015 / Revised: 2 Nov. 2015 / Accepted: 7 Dec. 2015 / Published: 8 Jan. 2016

Index Terms

Buffer, BiCMOS, High load, Capacitor, Low power, Inverter


BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

Cite This Paper

Maede Kaviani, Hojjat Sharifi, Mahdi Dolatshahi, Keivan Navi,"Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor", International Journal of Engineering and Manufacturing(IJEM), Vol.6, No.1, pp.1-9, 2016. DOI: 10.5815/ijem.2016.01.01


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