Combining Near Field Communication (NFC) technology with Secure Hash Algorithm (SHA) 256-bit encryption into smart homes may offer new opportunities to improve the security and usability of today’s homes. The goal of this paper is to explore a new way to automate home functions using NFC to authenticate users and share information seamlessly, while also using SHA 256-bit for secure encryption of sensitive information. By using this combined technology, homeowners will be able to securely operate their smart home devices through NFC-enabled Smartphone’s or wearable devices rather than having to remember complicated passwords or use complicated authentication methods. Because all communications between each user’s device and the smart home hub will be securely encrypted with SHA 256, protected from unauthorized access or tampering, the transferred data will be both confidential and have its integrity preserved. Additionally, because of the flexibility of the described system, it will be possible to easily integrate existing smart homes into a single platform and support users in many different applications, such as home security, energy management, remote monitoring, etc. Performance testing and validation will continue throughout this process. Then we demonstrate the way technology presented in this paper has improved both security and user experience in a smart home environment. The research presented will advance the technology used in smart homes through the use of NFC with SHA-256-based hashing for integrity and authentication to create a stable and user friendly method for providing security, as well as efficiency, in home automation.

Hand-drawn circuit diagrams must be manually converted into hardware description languages (HDLs) for digital design workflows. This manual conversion is time-consuming and error-prone and there has been little focus on hardware validation along the entire end-to-end circuit design process (such as circuit recognition and code generation). In response to these challenges, we present Sketic-FPGA, an end-to-end machine learning-based automated framework for converting hand-drawn logic circuits into functionally verified implementations on FPGA devices. The Sketic-FPGA system operates in a six-stage pipeline consisting of: adaptive image preprocessing, gate detection using an improved Faster R-CNN with ResNet-50 backbone, topology extraction, synthesis-aware Verilog code generation, automated FPGA implementation using Xilinx Vivado toolchain, and hardware-level validation. The proposed model was trained with 800 annotated samples across eight classes of logic gates, utilizing rotation-aware detection and curriculum learning to improve robustness. When evaluated against a dataset of 200 previously-unseen, test circuits, Sketic-FPGA produced 99.2% detection accuracy and 98.8% classification accuracy. All designs generated with Sketic-FPGA were successfully synthesized and implemented onto actual FPGA hardware, achieving functional correctness across the entire test circuit dataset using LED testing, Integrated Logic Analyzer (ILA) waveform verification, and exhaustive truth-table validation. On average, processing each circuit took 29.4 seconds from start to finish which has reduced the time required for a designer to create a circuit manually. An examination of how long it took students to design a circuit revealed that they spent 67% less time across multiple design iterations. Although we have only demonstrated the effectiveness of our framework on combinational circuits and in a controlled environment, our results indicate that there are many opportunities for rapid prototyping and automated hardware design as well as support for digital educational methods.