Inturu Bhavani Siva Phanindra; Shaik Hasane Ahammad; J. Sivavara Prasad; Saggurthi Spandana; Ahmed Nabih Zaki Rashed

Sketic-FPGA: A Complete Machine Learning-Based Platform for Hand-Drawn Circuit Recognition and Hardware Implementation

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Author(s)

Inturu Bhavani Siva Phanindra ¹ Shaik Hasane Ahammad ¹ J. Sivavara Prasad ² Saggurthi Spandana ¹ Ahmed Nabih Zaki Rashed ^3,*

1. Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Andhra Pradesh, India-522302

2. Department of EEE, Lakireddy Bali Reddy College of Engineering, Mylavaram, India-521230

3. Electronics and Electrical Communications Engineering Department, Faculty of Electronic Engineering, Menouf 32951, Menoufia University, Egypt

* Corresponding author.

DOI: https://doi.org/10.5815/ijem.2026.03.16

Received: 22 Jan. 2026 / Revised: 25 Feb. 2026 / Accepted: 12 Apr. 2026 / Published: 8 Jun. 2026

Index Terms

Xilinx Vivado, digital circuit recognition, FPGA implementation, machine learning, Verilog synthesis, Hardware validation

Abstract

Hand-drawn circuit diagrams must be manually converted into hardware description languages (HDLs) for digital design workflows. This manual conversion is time-consuming and error-prone and there has been little focus on hardware validation along the entire end-to-end circuit design process (such as circuit recognition and code generation). In response to these challenges, we present Sketic-FPGA, an end-to-end machine learning-based automated framework for converting hand-drawn logic circuits into functionally verified implementations on FPGA devices. The Sketic-FPGA system operates in a six-stage pipeline consisting of: adaptive image preprocessing, gate detection using an improved Faster R-CNN with ResNet-50 backbone, topology extraction, synthesis-aware Verilog code generation, automated FPGA implementation using Xilinx Vivado toolchain, and hardware-level validation. The proposed model was trained with 800 annotated samples across eight classes of logic gates, utilizing rotation-aware detection and curriculum learning to improve robustness. When evaluated against a dataset of 200 previously-unseen, test circuits, Sketic-FPGA produced 99.2% detection accuracy and 98.8% classification accuracy. All designs generated with Sketic-FPGA were successfully synthesized and implemented onto actual FPGA hardware, achieving functional correctness across the entire test circuit dataset using LED testing, Integrated Logic Analyzer (ILA) waveform verification, and exhaustive truth-table validation. On average, processing each circuit took 29.4 seconds from start to finish which has reduced the time required for a designer to create a circuit manually. An examination of how long it took students to design a circuit revealed that they spent 67% less time across multiple design iterations. Although we have only demonstrated the effectiveness of our framework on combinational circuits and in a controlled environment, our results indicate that there are many opportunities for rapid prototyping and automated hardware design as well as support for digital educational methods.

Cite This Paper

Inturu Bhavani Siva Phanindra, Shaik Hasane Ahammad, J. Sivavara Prasad, Saggurthi Spandana, Ahmed Nabih Zaki Rashed, "Sketic-FPGA: A Complete Machine Learning-Based Platform for Hand-Drawn Circuit Recognition and Hardware Implementation", International Journal of Engineering and Manufacturing (IJEM), Vol.16, No.3, pp.270-286, 2026. DOI:10.5815/ijem.2026.03.16

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International Journal of Engineering and Manufacturing (IJEM)