Work place: Electronics and Communication Engineering Department, BMS College of Engineering, Bangalore, Karnataka, India
E-mail: gpoornima.ece@bmsce.ac.in
Website:
Research Interests:
Biography
Poornima G. , Professor in the Department of Electronics and Communication Engineering is a committed academician with over 26 years of experience in B.M.S. College of Engineering. She obtained her Bachelor of Engineering in Electronics & Communication Engineering from Bangalore Institute of Technology and received her Master’s degree in Digital Communication Engineering from BMS College of Engineering. She holds a PhD in the Energy Efficient and fault tolerant Wireless Sensor Networks from University Visvesvaraya College of Engineering, Bangalore University, Bengaluru, Karnataka, India. Her research interest includes Energy Efficient Computer Networks, Fault Tolerant Signal Processing, and Energy Harvesting in Wireless Sensor Networks. She has an extensive experience in designing curriculum, developing education pedagogy. She has published over 45 research papers, 3 Patents and edited course materials. She has developed courses for Program-16 and Program-17 and assisted VTU in delivering education through satellite for Courses Analog Communication, Antenna and Wave Propagation and developed course modules for the e-shishana Program 5 for the course Analog Electronics, GIAN-Global Initiative for Academic Networking Course on r “Towards Safe Cities:A Mobile and Social networking Approach”. She has fetched grants from MHRD, DRDO, TEQIP Bengaluru. She was the Organizing Chair of the IEEE First International Conference on Networking Embedded and Wireless Systems-2018. She has severed as an evaluator/advisor in several evaluation committees constituted by UPSC, AICTE, KPSC, VTU, KEA. She is an IEEE Senior Grade Member, Fellow IETE and a Life Member of ISTE, Life Member AIMEE. She was awarded with Adarsh Vidya Saraswati Rashtriya Puraska in 2018 and Excellence in Higher Education in the year 2019 from the Center of Leadership Development, Venus International Foundation and Distinguish Professor Award from Lance Research Institute, LRI International Award in the Year 2024.
DOI: https://doi.org/10.5815/ijem.2025.04.04, Pub. Date: 8 Aug. 2025
This project presents an architecture for approximate matching in Content Addressable Memory (CAM) systems, which are essential for search-intensive applications such as networking and genomic analysis. Traditional CAM designs often suffer from high power consumption and reduced performance. To address these challenges, this work proposes a low complexity sensing scheme that integrates transmission gate logic and a modified inverter architecture using the SAPON technique. The primary objective is to improve power efficiency and write ability in CAM systems. By incorporating the SAPON technique, the design significantly reduces power consumption, enhancing energy efficiency while maintaining high-speed functionality. Transmission gate logic improves write ability, facilitating smoother data operations, particularly in applications requiring approximate matching. The proposed design is thoroughly validated through extensive simulation using the GPDK 45nm library in Cadence Virtuoso. The results show substantial reductions in power consumption and delay, alongside improvements in performance. The optimized CAM architecture demonstrates high tolerance for mismatches, making it ideal for applications such as DNA sequencing and network routing. This CAM design provides a scalable and energy efficient solution for modern computing environments, where performance and low power consumption are critical. Overall, this design offers a reliable and energy-efficient solution for accelerating search operations in data-driven fields, positioning it as an advancement in content-addressable memory technology.
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