Work place: IC Design Group CSIR-Central Electronics Engineering Research Institute, Pilani - 333031, Rajasthan, India.
Research Interests: Embedded System, Computer systems and computational processes
Anil Kumar Saini is working as Scientist in CSIR-Central Electronics Engineering Research Institute, Pilani, Rajasthan, India. He is Member of IEEE – USA and IACSIT – Singapore. His research interests include Analog and Mixed Signal Design, Embedded System Design, and CMOS RF IC design. Prior to joining this research lab, he worked in Cadence, India. He received his Master in Technology and Master in Science in 2003 and 2000 respectively from IIT Roorkee, India.
DOI: https://doi.org/10.5815/ijigsp.2017.02.07, Pub. Date: 8 Feb. 2017
This paper presents the design and implementation of a dedicated hardware (VLSI) architecture for real-time object tracking. In order to realize the complete system, the designed VLSI architecture has been integrated with different input/output video interfaces. These video interfaces along with the designed object tracking VLSI architecture have been coded using VHDL, simulated using ModelSim, and synthesized using Xilinx ISE tool chain. A working prototype of complete object tracking system has been implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board. The implemented system is capable of tracking the moving target object in real-time in PAL (720x576) resolution live video stream directly coming from the camera. Additionally, the implemented system also provides the real-time desired camera movement to follow the tracked object over a larger area.[...] Read more.
DOI: https://doi.org/10.5815/ijigsp.2014.04.04, Pub. Date: 8 Mar. 2014
Advances in FPGA technology have dramatically increased the use of FPGAs for computer vision applications. The primary task for development of such FPGAs based systems is the interfacing of the analog camera with FPGA board. This paper describes the design and implementation of camera interface module required for connecting analog camera with Xilinx ML510 (Virtex–5 FXT) FPGA board having no video input port. Digilent VDEC1 video daughter card is used for digitizing the analog video into digital form. The necessary control logics for video acquisition and video display are designed using VHDL and Verilog, simulated in ModelSim, and synthesized using Xilinx ISE 12.1. Designed and implemented interfaces provide the real-time video acquisition and display.[...] Read more.
DOI: https://doi.org/10.5815/ijigsp.2013.05.07, Pub. Date: 28 Apr. 2013
Image scaling, fundamental task of numerous image processing and computer vision applications, is the process of resizing an image by pixel interpolation. Image scaling leads to a number of undesirable image artifacts such as aliasing, blurring and moiré. However, with an increase in the number of pixels considered for interpolation, the image quality improves. This poses a quality-time trade off in which high quality output must often be compromised in the interest of computation complexity. This paper presents a comprehensive study and comparison of different image scaling algorithms. The performance of the scaling algorithms has been reviewed on the basis of number of computations involved and image quality. The search table modification to the bicubic image scaling algorithm greatly reduces the computational load by avoiding massive cubic and floating point operations without significantly losing image quality.[...] Read more.
DOI: https://doi.org/10.5815/ijigsp.2012.12.03, Pub. Date: 8 Nov. 2012
Color Image edge detection is very basic and important step for many applications such as image segmentation, image analysis, facial analysis, objects identifications/tracking and many others. The main challenge for real-time implementation of color image edge detection is because of high volume of data to be processed (3 times as compared to gray images). This paper describes the real-time implementation of Sobel operator based color image edge detection using FPGA. Sobel operator is chosen for edge detection due to its property to counteract the noise sensitivity of the simple gradient operator. In order to achieve real-time performance, a parallel architecture is designed, which uses three processing elements to compute edge maps of R, G, and B color components. The architecture is coded using VHDL, simulated in ModelSim, synthesized using Xilinx ISE 10.1 and implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA platform. The complete system is working at 27 MHz clock frequency. The measured performance of our system for standard PAL (720x576) size images is 50 fps (frames per second) and CIF (352x288) size images is 200 fps.[...] Read more.
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