K. Venkateswara Rao

Work place: Centre for Nano science and Technology, Jawaharlal Nehru Technological University Hyderabad

E-mail: vrkatevarapu@gmail.com

Website: https://orcid.org/0000-0002-9364-2461

Research Interests: Bioinformatics, Computational Biology


K. Venkateswara Rao – Dr. K. Venkateswara Rao completed his M.Sc. (Physics) from Central University of Hyderabad in the year 1997 and is a gold medallist. He was UGC-CSIR (NET) qualified in the year 2001 and was awarded his Ph.D. from Central University of Hyderabad in the year 2008. He completed his M.Tech. in Computer Science Engineering from Jawaharlal Nehru Technological University Hyderabad and is presently working as Associate Professor in Nano Technology at CNST, JNT University Hyderabad. He has several research publications in international & national journals, national & international conferences and also conducted many workshops. He is recognized as DST committee member, BOS chairman for B.Tech – Mechanical Engineering (Nano Technology), Red Cross Life member, BOS member at JNTUH (physics), JNTUK (physics), JNTUA (physics), KL University (NanoTechnology). Dr. K. Venkateswara Rao is also member of Nano Technology subcommittee, Andhra Pradesh Chambers of Commerce and Industry (FAPCCI), regular writer for first year B.Tech Engineering physics material for sakshi, bavitha website and guest faculty of National institute of fashion technology. He has guided more than 60 PG projects, supervising 8 Ph.D. students and is also working on the projects which are funded by UGC and DST-SERB. His current areas of research specialization include Synthesis of and characterization of nano materials, fabrication of thin films and characterization, bio-Medical application of nano materials, DMS nano materials, Pulsed electro fabrication on silicon substrate nano lanthana and characterization for future CMOS technology and Seed germination using nano materials.

Author Articles
Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction

By K.Bikshalu V.S.K. Reddy M.V. Manasa K. Venkateswara Rao

DOI: https://doi.org/10.5815/ijem.2014.03.02, Pub. Date: 18 Dec. 2014

Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.

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