Work place: Department of ECE, Kakatiya University, Warangal

E-mail: kalagaddaashu@gmail.com


Research Interests: Computer Architecture and Organization


Bikshalu – Mr. K. Bikshalu completed his B.Tech. in Electronics and Communication Engineering and M.Tech with the specialization of Digital Electronics and Communication Engineering. He was appointed as Assistant Professor in department of ECE at Kakatiya University, Warangal, India in the year 2008. He guided many B.Tech. and M.Tech. projects in his service and now about to obtain his Ph.D. from Jawaharlal Nehru Technological University Hyderabad, India. Mr. K. Bikshalu published several research papers in peer reviewed journals and conferences and participated in several workshops. His area of expertise and present research is oriented towards Nanotechnology, VLSI and Digital Electronics

Author Articles
Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction

By K.Bikshalu V.S.K. Reddy M.V. Manasa K. Venkateswara Rao

DOI: https://doi.org/10.5815/ijem.2014.03.02, Pub. Date: 18 Dec. 2014

Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.

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