M.V. Manasa

Work place: Centre for Nano science and Technology, Jawaharlal Nehru Technological University Hyderabad



Research Interests: Theory of Computation, Speech Synthesis


M.V. Manasa – M.V. Manasa completed her B.Tech in Electronics and Communication Engineering and M.Tech in Nano Technology from Jawaharlal Nehru Technological University Hyderabad. She worked on synthesis and simulation of high K dielectric materials and has publications in many peer reviewed national and international journals. She is recently awarded by DST-INSPIRE Fellowship and her present research is oriented towards synthesis, characterization of nano lanthanides, MOSFET and nano electronic devices simulation studies.

Author Articles
Simulation Studies of Silica and High K Oxide Contained MOS Circuits (45nm, 32nm and 22nm) for Power Dissipation Reduction

By K.Bikshalu V.S.K. Reddy M.V. Manasa K. Venkateswara Rao

DOI: https://doi.org/10.5815/ijem.2014.03.02, Pub. Date: 18 Dec. 2014

Advances in semiconductor technology lead to the advancements in integrated circuits which have enhanced performance, reliability, cost effective, low power consumption, etc. To build a complex digital circuitry, millions of transistors are to be embedded onto a single chip to increase the performance and to improve the reliability of the electronic device. This paper aims at building of N-MOSFET, P-MOSFET, CMOS inverter and NAND gate using conventional SiO2 oxide layer and high k oxide layer each of 45nm, 32nm and 22nm technologies respectively and to determine the percentage reduction in power dissipation using high k oxide layer in each device. The above mentioned devices are built using an online Predictive Technology Model tool and H-Spice simulation software and the simulated results are compared.

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