Ramin Rajaei

Work place: Department of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

E-mail: r_rajaei@sbu.ac.ir


Research Interests: Computational Science and Engineering


Ramin Rajaei received the MSc and Ph.D. degrees both in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2009 and 2014 respectively. He joined the department of electrical engineering at Shahid Beheshti University in 2015, where he currently is an assistant professor. His research interest includes reliable nano-scale systems design, low power and fault-tolerant embedded systems and computer architecture.

Author Articles
A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

By Nastaran Rajaei Ramin Rajaei

DOI: https://doi.org/10.5815/ijmecs.2016.09.03, Pub. Date: 8 Sep. 2016

This article proposes a radiation hardened parallel IO port capable of tolerating radiation induced soft errors including single event upsets (SEUs) as well as single event transients (SETs). To investigate the soft error tolerance capability of the proposed design, we simulated it using the Cadence tool and showed its offered advantages. Comparing with the conventional and well-known TMR IO port, the proposed architecture results in less hardware redundancy and design cost. Through an analytical analysis, we also showed that, our design has lower failure probability than the TMR approach. It also is notable that, among the considered previous counterparts, our proposed design is the only one that is capable of tolerating both the SEUs and SETs.

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Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

By Ramin Rajaei

DOI: https://doi.org/10.5815/ijem.2016.05.02, Pub. Date: 8 Sep. 2016

In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed. This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit masking in every triad of bits while the TMR structure, only masks one fault in a triad.
We implemented a 64-bit register file comprised of 64 registers protected with the proposed PBUM technique on FPGA. Our simulation results reveal that, over the TMR and some Hamming code-based techniques, our design offers a very higher robustness against radiation induced soft errors. Also, the proposed PBUM technique imposes a lower delay than its counterparts at the expense of a little higher area overhead. To reduce the area overhead, an area-efficient strategy is suggested that balances the reliability improvement and the area overhead. We show that, our technique using this area-aware strategy still has the highest reliability among the other considered techniques.

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