Nastaran Rajaei

Work place: Department of Computer Engineering, Birjand University, Birjand, Iran



Research Interests:


Nastaran Rajaei received the BSc degree in computer engineering from Birjand University, Birjand, Iran in 2015. Her research interest includes fault tolerance and fault modeling in CMOS VLSI design and also new emerging technologies.

Author Articles
A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

By Nastaran Rajaei Ramin Rajaei

DOI:, Pub. Date: 8 Sep. 2016

This article proposes a radiation hardened parallel IO port capable of tolerating radiation induced soft errors including single event upsets (SEUs) as well as single event transients (SETs). To investigate the soft error tolerance capability of the proposed design, we simulated it using the Cadence tool and showed its offered advantages. Comparing with the conventional and well-known TMR IO port, the proposed architecture results in less hardware redundancy and design cost. Through an analytical analysis, we also showed that, our design has lower failure probability than the TMR approach. It also is notable that, among the considered previous counterparts, our proposed design is the only one that is capable of tolerating both the SEUs and SETs.

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