Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

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Ramin Rajaei 1,*

1. Department of Electrical Engineerimg, Shahid Beheshti Univeristy, Tehran, PO BOX: 1983963113, Iran

* Corresponding author.


Received: 19 May 2016 / Revised: 24 Jun. 2016 / Accepted: 5 Aug. 2016 / Published: 8 Sep. 2016

Index Terms

Triple Modular Redundancy (TMR), Single Event Upset (SEU), Multiple Bit Upset (MBU), Register File, Fault Tolerance


In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed. This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit masking in every triad of bits while the TMR structure, only masks one fault in a triad.
We implemented a 64-bit register file comprised of 64 registers protected with the proposed PBUM technique on FPGA. Our simulation results reveal that, over the TMR and some Hamming code-based techniques, our design offers a very higher robustness against radiation induced soft errors. Also, the proposed PBUM technique imposes a lower delay than its counterparts at the expense of a little higher area overhead. To reduce the area overhead, an area-efficient strategy is suggested that balances the reliability improvement and the area overhead. We show that, our technique using this area-aware strategy still has the highest reliability among the other considered techniques.

Cite This Paper

Ramin Rajaei,"Design of a Radiation Hardened Register File for Highly Reliable Microprocessors", International Journal of Engineering and Manufacturing(IJEM), Vol.6, No.5, pp.11-21, 2016. DOI: 10.5815/ijem.2016.05.02


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