As classical computation approaches its fundamental limits related to power dissipation, reversible logic, which theoretically achieves zero energy loss, is becoming a critical technology for future low-power and quantum computing. However, most research in this field remains theoretical, lacking practical, hardware-verified implementations. This paper bridges this gap by presenting the complete hardware implementation and rigorous fault-tolerance validation of a reversible encryptor based on extended Fredkin gates. First, we detail the full realization of the encryptor on an Altera Cyclone IV Field-Programmable Gate Array. This implementation is not just a simulation but a complete, interactive hardware prototype, featuring real-time data input via a standard keyboard and output to a video graphics array monitor. Second, since functional verification is insufficient for cryptographic hardware and exhaustive testing is computationally infeasible, we introduce a novel validation methodology. This core contribution utilizes a metaheuristic ant colony optimization algorithm, not for synthesis, but for the intelligent generation of an optimal and compact set of test vectors. This test set is designed to achieve maximum fault coverage for the industry-standard "stuck-at fault" model. The algorithm successfully generated a minimal test set achieving 100% coverage for the considered single stuck-at fault model. We then experimentally validated this methodology by manually injecting a stuck-at fault into the hardware description language, recompiling the faulty circuit into the device, and confirming that the metaheuristically generated test vector successfully detected the physical fault. Thus, this work demonstrates the full cycle from theory to a practically validated and reliable hardware implementation of a reversible system.