International Journal of Information Technology and Computer Science (IJITCS)
IJITCS Vol. 18, No. 3, 8 Jun. 2026
Cover page and Table of Contents: PDF (size: 1547KB)
FPGA Implementation of a Fault-tolerant Encryptor Based on Reconfigurable Fredkin Gates
PDF (1547KB), PP.1-12
Views: 0 Downloads: 0
Author(s)
Taras Kyryliuk
1,*
Mykhailo Palahuta
1
Oleksii Dovhaniuk
2
Vitaly Deibuk
1
Index Terms
Reversible Logic, Ant Colony Optimization (ACO), Simulation, Fault Tolerance, Test Vector Generation, FPGA, Stuck-at Fault, Fredkin Gate, Model
Abstract
As classical computation approaches its fundamental limits related to power dissipation, reversible logic, which theoretically achieves zero energy loss, is becoming a critical technology for future low-power and quantum computing. However, most research in this field remains theoretical, lacking practical, hardware-verified implementations. This paper bridges this gap by presenting the complete hardware implementation and rigorous fault-tolerance validation of a reversible encryptor based on extended Fredkin gates. First, we detail the full realization of the encryptor on an Altera Cyclone IV Field-Programmable Gate Array. This implementation is not just a simulation but a complete, interactive hardware prototype, featuring real-time data input via a standard keyboard and output to a video graphics array monitor. Second, since functional verification is insufficient for cryptographic hardware and exhaustive testing is computationally infeasible, we introduce a novel validation methodology. This core contribution utilizes a metaheuristic ant colony optimization algorithm, not for synthesis, but for the intelligent generation of an optimal and compact set of test vectors. This test set is designed to achieve maximum fault coverage for the industry-standard "stuck-at fault" model. The algorithm successfully generated a minimal test set achieving 100% coverage for the considered single stuck-at fault model. We then experimentally validated this methodology by manually injecting a stuck-at fault into the hardware description language, recompiling the faulty circuit into the device, and confirming that the metaheuristically generated test vector successfully detected the physical fault. Thus, this work demonstrates the full cycle from theory to a practically validated and reliable hardware implementation of a reversible system.
Cite This Paper
Taras Kyryliuk, Mykhailo Palahuta, Oleksii Dovhaniuk, Vitaly Deibuk, "FPGA Implementation of a Fault-tolerant Encryptor Based on Reconfigurable Fredkin Gates", International Journal of Information Technology and Computer Science(IJITCS), Vol.18, No.3, pp.1-12, 2026. DOI:10.5815/ijitcs.2026.03.01
Reference
[1]R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Research & Development, Vol. 5, No. 3, pp. 183-191, 1961.
[2]A. Bérut, A. Petrosyan, and S. Ciliberto, "Information and thermodynamics: experimental verification of Landauer’s erasure principle," Journal of Statistical Mechanics: Theory and Experiment, Vol. 2015, No. 6, pp. P06015, 2015.
[3]Z. Hu, V. Deibuk, “Design of ternary reversible/quantum sequential elements,” Journal of Thermoelectricity, No. 1, pp. 5 – 17, 2018.
[4]V. Deibuk, O. Dovhaniuk, and T. Kyryliuk, "The extended Fredkin gates with reconfiguration," Lecture Notes on Data Engineering and Communications Technologies, Vol. 181, pp. 95-105, 2023. DOI: 10.1007/978-3-031-36118-0_9.
[5]G. Thakur, S. Keshri and K. Chaudhari, "Design of Energy Efficient 16-Bit Reversible ALU for Low Power IoT Applications," 2025 12th Int. Conf. on Computing for Sustainable Global Development (INDIACom), Delhi, India, 2025, pp. 1-6. DOI: 10.23919/INDIACom66777.2025.11115804.
[6]O. Dovhaniuk, T. Kyryliuk, and V. Deibuk, "Reversible Fault-Tolerant Encryption Using Extended Fredkin Gate With Reconfiguration," Advances in Transdisciplinary Engineering, Vol. 65, pp. 69 – 76. 2025. DOI: 10.3233/ATDE250113
[7]K. Rajesh and G. Umamaheswara Reddy, "FPGA implementation of encryption and decryption of a message using optimized reconfigurable reversible gate," International Journal of Recent Technology and Engineering (IJRTE), Vol. 8, No. 2, pp. 1654-1658, 2019.
[8]M. Bryk, K. Gracki, P. Kerntopf, M. Pawłowski, and A. Skorupski, "Encryption Using Reconfigurable Reversible Logic Gate and Its Simulation in FPGAs," in Proc. 23rd Int. Conf. "Mixed Design of Integrated Circuits and Systems" (MIXDES 2016), Łódź, Poland, 2016, pp. 203-206.
[9]R. Wille and R. Drechsler, "BDD-based synthesis of reversible logic," International Journal of Applied Metaheuristic Computing (IJAMC), Vol. 1, No. 4, pp. 25–41, 2010.
[10]Y. Kimura, S. Li, H. Sato, M. Fujita and R. Wille, "Improving Decision Diagram-Based Quantum Circuit Simulation Using Static Variable Ordering and Multinode Ring Communication," IEEE Transactions on Quantum Engineering, Vol. 7, 2500315, 2026. https://doi.org/10.1109/TQE.2026.3654543.
[11]D. Maslov, G. W. Dueck, and D. M. Miller, "Synthesis of Fredkin–Toffoli reversible networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp. 765-769, 2005.
[12]T. N. Sasamal, A. K. Singh, and A. Mohan, "Reversible Logic Circuit Synthesis and Optimization using Adaptive Genetic Algorithm," Procedia Computer Science, Vol. 70, pp. 407-413, 2015.
[13]D. Volpe, G. Orlandi, and G. Turvani, "Improving the Solving of Optimization Problems: A Comprehensive Review of Quantum Approaches," Quantum Reports, Vol. 7, No. 1: 3, 2025. https://doi.org/10.3390/quantum7010003.
[14]X. Wang et al., "Hybrid Encoding Evolutionary Algorithm for Reversible Logic Synthesis," Journal of Physics: Conference Series, Vol. 2504, 012040, 2023.
[15]J. Han, X. Zhang, and X. Wang, "Application Research of Evolutionary Algorithm in Synthesis of Reversible Logic Circuits," Journal of Physics: Conference Series, Vol. 1237, 022083, 2019.
[16]A. Rajput, R. Kumawat, A. Srinivasulu, et al. Robust and compact reversible logic gate for low-power and high-performance computing. Sci Rep Vol. 16, 154, 2026. https://doi.org/10.1038/s41598-025-29369-5.
[17]M. Li, Y. Zheng, M. S. Hsiao, and C. Huang, "Reversible logic synthesis through ant colony optimization," in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp. 208-212.
[18]K. Podlaski, "Ant Colony Optimization Implementation for Reversible Synthesis in Walsh-Hadamard Domain," Lecture Notes in Computer Science, Vol 12141, 4370, 2020.
[19]T. Kyryliuk, M. Palahuta, and V. Deibuk, "Using artificial intelligence methods for the optimal synthesis of reversible networks," Radioelectronic and computer systems, No. 4, pp. 117-126, 2024.
[20]O. Dovhaniuk, and V. Deibuk "Synthesis and Implementation of Reconfigurable Reversible Generalized Fredkin Gate," in Proc. 2021 IEEE XIIth Int. Conf. on Electronics and Information Technologies (ELIT), 2021, pp. 165-169.
[21]B. Murali Krishna, K. C. Sri Kavya, P. V. S. Sai Kumar, K. Karthik, and Y. Siva Nagababu, "FPGA implementation of image cryptology using reversible logic gates," International Journal of Advanced Trends in Computer Science and Engineering, Vol. 9, No. 3, pp. 2522-2526, 2020.
[22]A. Patel, I. L. Markov, and J. P. Hayes, "Fault testing for reversible circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 8, pp. 1220-1230, 2004.
[23]D. Kheirandish, M. Haghparast, M. Reshadi, and M. Hosseinzadeh, "Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit," Quantum Information Processing, Vol. 20, No. 370, 2021.
[24]L. Burgholzer, R. Wille, "Exploiting Reversible Computing for Verification: Potential, Possible Paths, and Consequences", Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC '23), pp. 429–435, 2023.
[25]H. M. Gaur, A. K. Singh, and U. Ghanekar, "Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits", National Academy Science Letters, Vol. 44, pp. 215–220, 2021.
[26]R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, "RevLib: An Online Resource for Reversible Functions and Reversible Circuits," in Proc. 38th Int. Symp. on Multiple-Valued Logic (ISMVL), Dallas, TX, USA, 2008, pp. 220-225, 2008.