Work place: Electronics Technology Department, Guru Nanak Dev University, Amritsar, India
Research Interests: Neural Networks, Computer Networks
Sukhleen Bindra Narang received her PhD degree from Guru Nanak Dev University, Amritsar in the field of Electronics Technology and M. Tech from Indian Institute of Technology (IIT), Roorkee. She is presently working as Professor and Head in the Department of Electronics Technology, Guru Nanak Dev university,Amritsar. India. She has published number of research publications in reputed National and International journals and conferences and her current area of research are Microwave materials, neural networks, VLSI circuits.
DOI: https://doi.org/10.5815/ijieeb.2013.02.01, Pub. Date: 8 Aug. 2013
The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered from the previous work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLAB, which can be used as a cost estimation tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimation tools for test planning.[...] Read more.
Subscribe to receive issue release notifications and newsletters from MECS Press journals