Cost Modeling for SOC Modules Testing

Full Text (PDF, 234KB), PP.1-7

Views: 0 Downloads: 0


Balwinder Singh 1,* Arun Khosla 2 Sukhleen B. Narang 3

1. Centre for Development of Advanced Computing (CDAC), Mohali, India

2. ECE Department Dr. B .R. Ambedkar National Institute of Technology, Jalandhar, India

3. Electronics Technology Department, Guru Nanak Dev University, Amritsar, India

* Corresponding author.


Received: 19 May 2013 / Revised: 10 Jun. 2013 / Accepted: 6 Jul. 2013 / Published: 8 Aug. 2013

Index Terms

Cost modeling, System on Chip, VLSI Testing, Cost Estimation Tool


The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered from the previous work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLAB, which can be used as a cost estimation tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimation tools for test planning.

Cite This Paper

Balwinder Singh, Arun Khosla, Sukhleen B. Narang, "Cost Modeling for SOC Modules Testing", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.5, no.2, pp.1-7, 2013. DOI:10.5815/ijieeb.2013.02.01


[1]International Technology Roadmap for Semiconductors (ITRS),” 2009. [Online]. Available:

[2]Ricardo Reis, Marcelo Lubaszewski, Jochen A.G. Jess Design of Systems on a Chip: Design and Test, Published by Springer, P.O. Box 17, 3300 AA Dordrecht, the Netherlands.

[3]Soo Ho Chang and Soo Dong Kim Reuse-based Methodology in Developing System-on-Chip (SOC) Proceedings of the Fourth International Conference on Software Engineering Research, Management and Applications (SERA’06)

[4]Dear, I.D., Dislis, C., Ambler, A.P., Dick, J. 1991. Economic effects in design and test, Design & Test of Computers, IEEE, vol.8 (4,):64-77.

[5]Andrew C. Evans, 1999. Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test, International Test Conference 1999 (ITC'99).

[6]Butler, K. M. 1999. Estimating the Economic Benefits of DFT. 16th IEEE Design. Test symposium 71-79.

[7]M. Abadir, A. Parikh, L. Bal, P. Sandborn, and C. Murphy, 1994. High Level Test Economics Advisor (Hi-TEA), Journal of Electronic Testing Theory and Practice, vol. 5, pp. 195–206.

[8]Karthik Sundararaman, Shambhu Upadhyaya, Martin Margala,” Cost Model Analysis of DFT Based Fault Tolerant SOC Designs,” 2004 IEEE.

[9]Li-Rong Zheng,” Cost and Performance Tradeoff Analysis in Radio and Mixed-Signal System-on-Package Design ,” IEEE Transactions on Advanced Packaging, Vol. 27, No. 2, May 2004.

[10]Songjun Lee and Anthony P. Ambler,” Cost Effective Test Planning For System-On-Chip Manufacture,” 2006 IEEE.

[11]Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges, 2002. Test Economics for Multi-site Test with Modern Cost Reduction Techniques, 20th IEEE VLSI Test Symposium, 411 – 416.

[12]Sudarshan Bahukudumbim, Sule Ozev, Krishnendu Chakrabarty, and Vikram Iyengar,” AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for “Big-D/Small-A” Mixed-Signal SOCs,” 2007 IEEE.

[13]Frank Vahid and Tony Givargis Embedded System Design: A Unified Hardware/Software Introduction John Wiley & Sons; 2002.

[14]juin-Ming Lu; Cheng-Wen Wu, "Cost and benefit models for logic and memory BIST," Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, vol., no., pp.710, 714, 2000.

[15]Nag, P.K.; Gattiker, A.; Sichao Wei; Blanton, R.D.; Maly, W., "Modeling the economics of testing: a DFT perspective," Design & Test of Computers, IEEE , vol.19, no.1, pp.29,41, Jan/Feb 2002.

[16]Kafrouni, M.; Thibeault, C.; Savaria, Y., "A cost model for VLSI/MCM systems," Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on , vol., no., pp.148,156, 20-22 Oct 1997.

[17]Sundararaman, K.; Upadhyaya, S.; Margala, M., "Cost model analysis of DFT based fault tolerant SOC designs," Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, vol., no., pp.465, 469, 2004.

[18]Kim, V., Chen, T., and Tegethoff, M., ASIC Manufac turing Test Cost Prediction at Early Design Stage. IEEE international Test conference (1997) 356-6.