Viranjay M. Srivastava

Work place: Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan - 173234, India

E-mail: Viranjay@ieee.org

Website:

Research Interests: Interaction Design, Computer systems and computational processes, Processor Design, Data Structures and Algorithms, Algorithm Design

Biography

Viranjay M. Srivastava received the Bachelor degree (2002) in Electronics and Instrumentation Engineering from the Rohilkhand University, Bareilly, India and the Master degree (2008) in VLSI design from Center for Development of Advanced Computing (C-DAC), Noida, India and Doctorate (2011) in the field of RF Microelectronics and VLSI Design from Jaypee University of Information Technology, Solan, Himachal Pradesh, India.

He was with the Semiconductor Process and Wafer Fabrication Center of BEL Laboratories, Bangalore, India, where he worked on characterization of MOS devices, fabrication of devices and development of circuit design. Currently he is a faculty in Jaypee University of Information Technology, Solan, Himachal Pradesh, India. His research and teaching interests includes VLSI design and CAD with particular emphasis in low-power design, Chip designing, VLSI testing and verification.

He has more than 8 years of teaching and research experience in the area of VLSI design, RFIC design, and Analog IC design. He has supervised a number of B. Tech. and M. Tech. theses. He is a member of IEEE, ACEEE and IACSIT. He has worked as a reviewer for several conferences and Journals both national and international. He is author of more than 50 scientific contributions including articles in international refereed Journals and Conferences and also author of two Books, 1) VLSI Technology, and 2) Characterization of C-V curves and Analysis, Using VEE Pro Software: After Fabrication of MOS Device.

Author Articles
Low Noise Amplifier for 2.45 GHz Frequency Band at 0.18 ┬Ám CMOS Technology for IEEE Standard 802.11 b/g WLAN

By Viranjay M. Srivastava Ravinder Kumar

DOI: https://doi.org/10.5815/ijisa.2012.09.09, Pub. Date: 8 Aug. 2012

This paper presents the design of low noise amplifier (LNA) at 2.45 GHz and integrated at 0.18 µm RF CMOS process technology. This type of LNA at 2.45 GHz is use in the Bluetooth receiver. The proposed method is useful to optimize noise performance and power gain while maintaining good input and output matching. The amplifier is designed to be used as first stage of a receiver for wireless communication. The main aim of designer is to achieve low noise figure with improved gain with the help of CMOS technology by using single stage n-MOS amplifier. The simulation results show a forward gain of 14.0 dB, a noise-figure of 0.5 dB and stability factor is approximate unity, in which the circuit operates at 14.2 mA drain current with supply voltage of 3.5 V and biasing voltage of 1.5 V.

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Analysis and Design of Tri-Gate MOSFET with High Dielectrics Gate

By Viranjay M. Srivastava Setu P. Singh

DOI: https://doi.org/10.5815/ijisa.2012.05.03, Pub. Date: 8 May 2012

The scaling of simple gate transistors requires the scaling and transistor elements like source/drain junction became difficult to scale further after a limit due to adverse effect of electrostatic and short-channel performance. The solution of the problem is tri-gate where we can increase the performance without increasing the width and without scaling. In this paper we have described the parameter of tri-gate and taking the high dielectric as substrate.

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