A. K Wadhwani

Work place: Department of Electrical Engineering, M.I.T.S. Gwalior, M.P., India

E-mail: wadhwani_arun@rediffmail.com


Research Interests: Computational Science and Engineering, Computational Engineering, Computing Platform, Engineering


A.K. Wadhwani received BE (Electrical) from Bhopal University, India in 1987 and ME (Measurement &  Instrumentation)  from University of Roorkee, India in 1993 and PhD. in Biomedical Instrumentation  from Indian Institute of Technology, Roorkee, India in 2003. He joined the Electrical Engineering Department of Madhav Institute of Technology & Science in 1988 as Lecturer. He has published more than 30 research papers and guided 25 PG students and supervised 03 and supervising 05 PhD theses. He has undertaken 04 research projects from various government agencies. He has also conducted faculty development program and conferences for the benefit of faculty and field engineers. He is the life member of IE Kolkata, India, ISTE, Delhi, India and IETE, Delhi, India. His areas of interest are Measurement & Instrumentation, Medical Instrumentation, and Digital Signal Processing and application of soft computing techniques in engineering.

Author Articles
Design of Fast Pipelined Multiplier using Modified Redundant Adder

By Rakesh Kumar Saxena Neelam Sharma A. K Wadhwani

DOI: https://doi.org/10.5815/ijisa.2012.04.07, Pub. Date: 8 Apr. 2012

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by reducing the number of gates. Due to reduction in gate count, number of gate levels and hence the circuit complexity is also reduced. As multiplication is repetitive addition, the implementation time of the multiplier circuit will also be reduced to a great extent by using modified design of adder cell to add the partial products. These partial products are added using pipelined units to reduce implementation time further. Thus with the use of proposed RBSD adder, other arithmetic operations such as subtraction, division, square root etc. can be performed much faster. It is concluded that efficiency of the proposed RBSD adder and multiplier is improved as compared to the techniques conventionally used in high speed machines. Thus the proposed modified RBSD adder cell using universal gates can be used to design fast ALU with many additional advantages.

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