Neelam Sharma

Work place: Department of Electronics and Communication Engineering, Institute of Engineering & Technology, Alwar, Rajasthan, India



Research Interests: Computer Networks, Computer Architecture and Organization, Neural Networks, Computer systems and computational processes


Neelam Sharma received the Ph.D. and M.Tech from U.P.T.U., Lucknow UP and B.E. from Thapar Institute of Engineering and Technology, Punjab India. She is Goldmedelist of Guru Nanak Dev University, Amritsar, Punjab, India in Pre engineering examination. Presently she is Professor in the Department of Electronics and Instrumentation Engineering, IET, Alwar, Raj. India. Her current research interests are Computer Architecture, Neural Networks, VLSI, FPGA, etc. She has twenty five research publications and convened number of sponsored research projects. She is member of IE Kolkata, India, IETE, Delhi, India and Computer Society of India. Presently she is working on various research projects funded by AICTE and World bank.

Author Articles
Design of Fast Pipelined Multiplier using Modified Redundant Adder

By Rakesh Kumar Saxena Neelam Sharma A. K Wadhwani

DOI:, Pub. Date: 8 Apr. 2012

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by reducing the number of gates. Due to reduction in gate count, number of gate levels and hence the circuit complexity is also reduced. As multiplication is repetitive addition, the implementation time of the multiplier circuit will also be reduced to a great extent by using modified design of adder cell to add the partial products. These partial products are added using pipelined units to reduce implementation time further. Thus with the use of proposed RBSD adder, other arithmetic operations such as subtraction, division, square root etc. can be performed much faster. It is concluded that efficiency of the proposed RBSD adder and multiplier is improved as compared to the techniques conventionally used in high speed machines. Thus the proposed modified RBSD adder cell using universal gates can be used to design fast ALU with many additional advantages.

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