Mythili. P

Work place: Division of Electronics, Cochin University of Science &Technology, Kochi, Kerala, India



Research Interests: Computer systems and computational processes, Image Compression, Image Manipulation, Image Processing, Combinatorial Optimization


Mythili.P was born at Marthandam, India on 16.07.1968. She completed her B.E degree from Madurai Kamaraj University, India in 1989, M.E and PhD degrees from College of Engineering, Guindy, Anna University, Chennai, India in the year 1991and 1999 respectively. She was a Post Doc with the University of Michigan in the year 2009-2010.She worked as a PROJECT ASSOCIATE at IIT, Chennai from 1991 -1992. She was a JRF/SRF with Anna university from 1994-1998. She Joined as LECTURER in Cochin University of Science and Technology in 1999.

Currently she continues as ASSOCIATE PROFESSOR with Cochin University of Science and Technology, Kochi, Kerala, India. She has around 19 publications in refereed journals and 40 National/ International conferences. Her research interests are in the areas of Signal Processing, Microwaves, Optimization techniques and Image processing. Dr. Mythili is a member of IEEE antennas and propagation, ISTE and IETE. She was awarded the prestigious BOYSCAST Fellowship by the Indian government to carry out post-doctoral research work at The University of Michigan the year 2009.

Author Articles
A Simplified Efficient Technique for the Design of Combinational Logic Circuits

By Vijayakumari C. K Mythili. P Rekha K James

DOI:, Pub. Date: 8 Aug. 2015

A new Genetic Algorithm based approach to the design of combinational logic circuits which uses only 2-1 multiplexers as the basic design unit has been proposed. To realize a function of n variables, conventional design needs 2n-1 units and n levels. Property of a multiplexer tree is that all the units in a level share the same control signal. In this paper, flexibility has been made in selecting the control signals so that units in the same level need not use the same select signal. Control signals can be any of the variables or functions derived from the immediate preceding level. Once a 100 % fit circuit is evolved, check for redundancy of units is made and redundant units are eliminated so that the circuit generated is optimal. It has been observed that the circuits evolved by this approach are superior to the circuits by conventional design in terms of area, power and delay. As power dissipation is an important metric in VLSI design, power loss can be minimized by eliminating unnecessary transitions/switching of idle multiplexers using a specific controller to select appropriate control signals. But in the proposed design power loss can be reduced without any additional device and hence these circuits can be recommended for low power devices.

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