A Simplified Efficient Technique for the Design of Combinational Logic Circuits

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Vijayakumari C. K 1,* Mythili. P 2 Rekha K James 2

1. Department of Electrical Engineering, Rajiv Gandhi Institute of Technology, Kottayam, Kerala, India

2. Division of Electronics, Cochin University of Science &Technology, Kochi, Kerala, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijisa.2015.09.06

Received: 17 Jan. 2015 / Revised: 11 Apr. 2015 / Accepted: 16 May 2015 / Published: 8 Aug. 2015

Index Terms

2-1multiplexer, Genetic Algorithm, Combinational Circuits, Shannon’s Decomposition


A new Genetic Algorithm based approach to the design of combinational logic circuits which uses only 2-1 multiplexers as the basic design unit has been proposed. To realize a function of n variables, conventional design needs 2n-1 units and n levels. Property of a multiplexer tree is that all the units in a level share the same control signal. In this paper, flexibility has been made in selecting the control signals so that units in the same level need not use the same select signal. Control signals can be any of the variables or functions derived from the immediate preceding level. Once a 100 % fit circuit is evolved, check for redundancy of units is made and redundant units are eliminated so that the circuit generated is optimal. It has been observed that the circuits evolved by this approach are superior to the circuits by conventional design in terms of area, power and delay. As power dissipation is an important metric in VLSI design, power loss can be minimized by eliminating unnecessary transitions/switching of idle multiplexers using a specific controller to select appropriate control signals. But in the proposed design power loss can be reduced without any additional device and hence these circuits can be recommended for low power devices.

Cite This Paper

Vijayakumari C. K, Mythili. P, Rekha K James, "A Simplified Efficient Technique for the Design of Combinational Logic Circuits", International Journal of Intelligent Systems and Applications(IJISA), vol.7, no.9, pp.42-48, 2015. DOI:10.5815/ijisa.2015.09.06


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