Dipak Marathe

Work place: A.C. Patil College of Engineering, Kharghar, 410210, India

E-mail: dsmarathe@acpce.ac.in


Research Interests: Communications, Wireless Communication, Wireless Networks


Dipak S. Marathe has submitted his Ph. D Thesis to University of Mumbai, and received the M. Tech. in Electronics from VJTI, Mumbai. He is currently Associate Professor in Electronics and Telecommunication Department at A. C. Patil College of Engineering, Navi-Mumbai, and Maharashtra, India. His research interests include Analog and Digital CMOS VLSI Design, and Wireless Communication.

Author Articles
COVID-19 Patient Health Monitoring System

By Anurag Tatkare Hemangi Patil Tejal Salunke Shreya Warang Dipak Marathe

DOI: https://doi.org/10.5815/ijem.2021.05.05, Pub. Date: 8 Oct. 2021

The system proposed can be used to regular checkup of the COVID patients while maintaining the social distancing. Also, the data sensed by the sensors is directly sent to doctor, reducing the cost of paying regular visits to doctor. The Iot platform used in the system helps to transfer the real time patient’s data remotely to host device. Daily health record can be maintained and can be viewed easily on graphs charts ease for doctors to see any abrupt changes in oxygen level or rise in temperature. To track the patient health micro-controller is in turn interfaced to an LCD display and wi-fi connection to send the data to the web-server (wireless sensing node). In case of any abrupt changes in patient heart-rate or body temperature alert is sent about the patient using IoT. This system also shows patients temperature and heartbeat tracked live data with timestamps over the Internetwork.

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A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

By Dipak Marathe Uday Pandit Khot

DOI: https://doi.org/10.5815/ijigsp.2019.11.06, Pub. Date: 8 Nov. 2019

This paper proposes a 10-bit mixed current mode low power SAR ADC for sensor node application. The different entities of a successive approximation register (SAR) analog-to-digital converter (ADC) circuit has a hybrid or mixed mode approach i.e.,voltage mode regenerative comparator; mixed SAR logic; and current mode digital-to-analog converter (DAC). The performance limitation of speed and the kick-back noise of a dynamic comparator is resolved using duty cycle controlled regenerative comparator. A mixed mode logic of a SAR is partitioning the design into synchronous ring counter and asynchronous output register. The data shifting of a ring counter is with the common clock tick while the output register exchanged it asynchronously using handshake signals, resulting in a low power SAR. The current mode switching function in a DAC to reduce asynchronous switching effect resulting in a low energy conversion per step. In overall, the proposed mixed SAR ADC consumes a 41.6  power and achieves an SFDR 69.3 dB at 10 MS/sec and 1 V supply voltage. It is designed and simulated in the 0.18 m TSMC CMOS process. 

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