Hansraj Guhilot

Work place: K.C.College of Engineering And Management Studies And Research, Thane (E), India

E-mail: hansraj.g@gmail.com


Research Interests: Engineering


Dr. Hansraj Guhilot, held many academic and R&D positions over a career span of 30 years, currently working as the Principal, K. C. College of engineering and management studies and research. He worked as Dean (R&D) and Professor of EC at KLE Dr. M. S.Sheshgiri College of Engineering and Technology, Belgaum, Karnataka. He has teaching experience spanning 28 years with a Ph.D. in Electronics, having thesis titled “Design and Development of CMOS Mixed-Mode Integrated circuit for Chloroplast Measurement” and Research work published in IEEE Sensors Journal. He is an IEEE Technical Paper Reviewer at IEEE International Conference on Recent Trends in Information, Telecommunication, and Computing (ITC), 2010. He is a member of Entrepreneur Development Cell (EDC) in Visveswaraya Technological University (VTU), Belgaum. He is a subject expert in CMOS VLSI, Edusat Program, VTU, and Belgaum. He has published 36 papers, delivered ten invited technical talks and is awarded with one US Patent and nine international patents. Worked as Director (R&D), Paradigm Industries Inc. USA and Consultant for N&N Allied Energy Services Inc. USA.

Author Articles
Design of an Arbiter for Two Systems Accessing a Single DDR3 Memory on a Reconfigurable Platform

By Arun S Tigadi Hansraj Guhilot

DOI: https://doi.org/10.5815/ijieeb.2018.06.02, Pub. Date: 8 Nov. 2018

The computer memory has been revolutionized in the last 25-30 years, in terms of both capacity and speed of execution. Along with this, even the logic controlling the memory has also become more and more complex and difficult to interface. Usually, memory subsystems will be designed to interact with a single system. Whenever we consider a two system is sharing a common memory, there comes the need for an Arbiter. The major difference between a memory arbiter and a processor scheduler is that the memory arbiter works at a much finer level of granularity. The time taken for the task execution may range from micro to milliseconds, while a RAM controller needs to serve the request in a few nanoseconds. Because of this reason the resource arbiters are usually designed and implemented in hardware rather than in software.

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Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform

By Arun Tigadi Hansraj Guhilot

DOI: https://doi.org/10.5815/ijem.2018.05.04, Pub. Date: 8 Sep. 2018

Multimedia applications play a very important role in the field of VLSI design and embedded systems. They need a large amount of memory storage with higher bandwidth and higher speed. To overcome this hazard, a memory controller is required. A memory controller is a device that stores the data and gives it back whenever required. Real-time recording of an audio data and finally storing it without losing the data is a difficult task. This paper describes the usage of Double Data Rate Synchronous Dynamic Random Access memory controller for storing the audio data. The design uses finite state machine (FSM) architecture that is developed for testing of this algorithm. Audio codec device is used for the conversion of analog data into digital and vice versa. The tool used to simulate this design is Xilinx ISE design suite. The hardware used to synthesize this design is FPGA Spartan-3 kit.

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