Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform

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Arun Tigadi 1,* Hansraj Guhilot 2

1. Department of E and C,KLE Dr. M.S.Sheshgiri College of Engineering and Technology, Belagavi,India

2. K.C.College of Engineering And Management Studies And Research, Thane (E), India

* Corresponding author.


Received: 21 May 2018 / Revised: 1 Jun. 2018 / Accepted: 18 Jun. 2018 / Published: 8 Sep. 2018

Index Terms

DDR2 SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), Audio Codec (coder-decoder), FPGA(Field Programmable Gate Array), UART(Universal Asynchronous Receiver and Transmitter)


Multimedia applications play a very important role in the field of VLSI design and embedded systems. They need a large amount of memory storage with higher bandwidth and higher speed. To overcome this hazard, a memory controller is required. A memory controller is a device that stores the data and gives it back whenever required. Real-time recording of an audio data and finally storing it without losing the data is a difficult task. This paper describes the usage of Double Data Rate Synchronous Dynamic Random Access memory controller for storing the audio data. The design uses finite state machine (FSM) architecture that is developed for testing of this algorithm. Audio codec device is used for the conversion of analog data into digital and vice versa. The tool used to simulate this design is Xilinx ISE design suite. The hardware used to synthesize this design is FPGA Spartan-3 kit.

Cite This Paper

Arun Tigadi, Hansraj Guhilot,"Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform", International Journal of Engineering and Manufacturing(IJEM), Vol.8, No.5, pp.32-48, 2018. DOI: 10.5815/ijem.2018.05.04


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