Archana Rani

Work place: Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India



Research Interests: Computational Science and Engineering, Computational Engineering, Engineering


Ms. Archana Rani Bhatia is a Ph.D. Scholar from Manav Rachna International University, Faridabad. Had completed Post Graduation in Electronics Product Design and Technology from Punjab Engineering College Chandigarh in 2008 and did Graduation in Electronics and Communication Engineering, with sound working experience over 6.6 years in various electronic works, related to Teaching, Research & Industry side.

Author Articles
Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado

By Archana Rani Naresh Grover

DOI:, Pub. Date: 8 Jul. 2018

As the technology era has been changing, the designing pattern of an IC is also changing. An IC de-signing is now divided into two definite fields i.e. Front-End design and Back-End design. The Front-End design is using HDLs (Hardware Description Languages i.e. VHDL or Verilog) and the verification of those ICs, whereas the Back-End Design is related to the Physical Design techniques. But both of the IC design techniques required some extra efforts in terms of their Speed, Shape, and Size, which needs the Optimization efforts. This pa-per deals with the area and power optimization efforts in terms of the logic utilization by using XST & Vivado Tools. After applying area optimization techniques i.e. Logic Optimization, LUT mapping and Resource Sharing etc. on already designed asynchronous microprocessor to be used as model for proposed optimization, reasonable results in terms of power and area utilization have been achieved.

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Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA

By Archana Rani Naresh Grover

DOI:, Pub. Date: 8 May 2018

In today’s fast growing world, the digital design domain has two dominant role factors i.e. the efficiency and speed. The design of asynchronous processor is used to reduce the various challenges faced in synchronous architectures. There are numerous advantages of asynchronous processors, especially in SOC (System on the chip), reducing the crosstalk between analog and digital circuits, easiness in multi-rate circuit integration, reusability of ease of component and at last the less power consumption. The objective of this research paper is to design and simulate control unit of the asynchronous processor by using Xilinx ISE tool in VHDL. A robust control unit has been designed using FPGA. This control unit is responsible for accumulating the whole processor functioning control at a single unit. This paper further presents the optimization techniques for reducing area power and delay constraints related to digital circuits using FPGA.

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Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA

By Archana Rani Naresh Grover

DOI:, Pub. Date: 8 Jan. 2018

As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.

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