Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA

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Archana Rani 1,* Naresh Grover 1

1. Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India

* Corresponding author.


Received: 29 Jan. 2018 / Revised: 22 Feb. 2018 / Accepted: 15 Mar. 2018 / Published: 8 May 2018

Index Terms

FPGA, Digital circuits, design optimization


In today’s fast growing world, the digital design domain has two dominant role factors i.e. the efficiency and speed. The design of asynchronous processor is used to reduce the various challenges faced in synchronous architectures. There are numerous advantages of asynchronous processors, especially in SOC (System on the chip), reducing the crosstalk between analog and digital circuits, easiness in multi-rate circuit integration, reusability of ease of component and at last the less power consumption. The objective of this research paper is to design and simulate control unit of the asynchronous processor by using Xilinx ISE tool in VHDL. A robust control unit has been designed using FPGA. This control unit is responsible for accumulating the whole processor functioning control at a single unit. This paper further presents the optimization techniques for reducing area power and delay constraints related to digital circuits using FPGA.

Cite This Paper

Archana Rani, Naresh Grover,"Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA", International Journal of Engineering and Manufacturing(IJEM), Vol.8, No.3, pp.12-22, 2018. DOI: 10.5815/ijem.2018.03.02


[1]I. Kuon and J. Rose, ―Measuring the Gap Between FPGAs and ASICs,‖ ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 21-30, 2006.

[2]Shackleford, B., Okushi, E., Yasuda, M., Koizumi, H., Seo, K.,Iwamoto, T., and Yasuura, H., “High-performance hardware design and implementation of genetic algorithms”, in Teodorescu et al, Hardware implementation of Intelligent Systems, pp. 53 - 87, 2001.

[3]Dick R.P., Jha N.K., MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software Cosynthesis of Distributed Embedded Systems, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 920-935, Oct. 1998.

[4]Jamro E., Wiatr K., Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution, Proc. Of the IEEE Int. Conf. Digital System Design, Warszawa, Poland, IEEE Computer Society Press, 4-6 Sep. 2001.

[5]Hassan, R., and Crossley, W., “Variable Population-Based Sampling for Probabilistic Design Optimization with a Genetic Algorithm,” AIAA-2004-0452, 42nd Aerospace Sciences Meeting, Reno, NV, January 2004.

[6]Hassan, R., Genetic Algorithm Approaches for Conceptual Design of Spacecraft Systems Including Multi Objective Optimization and Design under Uncertainty, doctoral thesis, Purdue University, May 2004. 

[7]G. Chen and J. Cong, “Simultaneous logic decomposition with technology mapping in FPGA designs”, in the Proceedings of the 2001 ACM/SIGDA ninth International Symposium on Field Programmable Gate Arrays, 2001, pp. 48-55.

[8]J. Cong and Y. Ding, “Flow Map: An Optimal Technology mapping algorithm for delay optimization in lookup-table based FPGA designs”, in IEEE Transactions on Computer-Aided Design and Integrated Circuits and Systems, Vol. 13, No. 1, January 1994, pp. 1-12.

[9]J. Cong and C. Wu, “An Efficient Algorithm for Performance-Optimal FPGA Technology Mapping with Retiming”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 9, September 1998, pp. 738-748.

[10]J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng, and J.Cong, “Bit-level optimization for high-level synthesis and FPGA-based acceleration,” in Proc. FPGA, Feb. 2010, pp. 59–68.