Mohammad Reza Reshadinezhad

Work place: Department of Computer Architecture, Faculty of Computer Engineering, University of Isfahan, Isfahan, 8174673441, Iran



Research Interests: Software Creation and Management, Software Development Process, Software Engineering, Software Organization and Properties, Logic Calculi, Logic Circuit Theory


Mohammad Reza Reshadinezhad was born in Isfahan, Iran, in 1959. He received his B.S. and M.S. degree from the Electrical Engineering Department of University of Wisconsin, Milwaukee, USA in 1982 and 1985, respectively. He has been in position of lecturer as faculty of computer engineering in University of Isfahan since 1991. He also received the Ph.D. Degree in computer architecture from Shahid Beheshti University, Tehran, Iran, in 2012. He is currently Assistant Professor in Faculty of Computer Engineering of Isfahan University. His research interests are Digital Arithmetic, Nanotechnology concerning CNFET, VLSI Implementation, Logic Circuits Design, and Cryptography.

Author Articles
Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology

By Parisa Nejadzadeh Mohammad Reza Reshadinezhad

DOI:, Pub. Date: 8 Apr. 2018

In this article a new design of a current mode full-adder is proposed through the field effect transistors based on carbon nanotubes. The outperformance of the current mode full-adder constructed by CNTFET compared to that of constructed by CMOS is observable in the simulation and comparisons. This circuit operates based on triple input majority function. The simulation is run by HSPICE software according to the model proposed in Stanford University for CNTFETs at 0.65 V power supply voltage. The proposed circuit outperforms compared to the previous current mode full-adders in terms of speed, accuracy and PDP.

[...] Read more.
A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

By Shekoofeh Moghimi Mohammad Reza Reshadinezhad

DOI:, Pub. Date: 8 Nov. 2015

This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.

[...] Read more.
Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

By Mohammad Reza Reshadinezhad Niloofar Charmchi Keivan Navi

DOI:, Pub. Date: 8 Sep. 2015

Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors’ levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit’s simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the three-operand multiplication done on computers nowadays, which we call it classical multiplier in this article.

[...] Read more.
Other Articles