Manisha Pattanaik

Work place: ICT Department, ABV-IIITM, Gwalior, India



Research Interests: Computer systems and computational processes, Information Systems, Data Structures and Algorithms


Dr. Manisha Pattanaik is currently working as Associate Professor in ICT department of ABV-IIITM Gwlaior. She is working with more than 75 Co-Researcher from Industry and Academia to create a globally educational excellence. She has authored and coauthored over 120 papers in journals and conference proceedings in various areas of VLSI design, applications and in Electronics Design Automation. She is a member of IEEE, ISTE Institute of Electronics, Information and Communication Engineers (IEICE), WSEAS.

Author Articles
Design and Analysis of Tunnel FET for Low Power High Performance Applications

By Umesh Dutta M.K.Soni Manisha Pattanaik

DOI:, Pub. Date: 8 Jan. 2018

Tunnel FET is a promising device to replace MOSFET in low power high performance applications. This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs1-xSbx-InAs) based TFET device. Simulations are performed using TCAD tool and simulation results suggest that conventional DGTFET device has less on current and degraded subthreshold slope as compared to InAs and III-V semiconductor based TFET device. InAs based TFET device provides steep subthreshold slope of 61 mV/dec and off current of the order of nano-amperes at sub 1V operation thereby making it an ideal choice for low power high performance applications. The variation in the performance of the III-V HTFET device with the variation in the mole fraction is also studied in detail. Carefully choosing the mole fraction value in III-V semiconductor based HTFET device can lead to better device performance.

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