Work place: Department of Electronics and Communication Engineering, FET, Manav Rachna International University, Faridabad, India

E-mail: pvc@mriu.edu.in


Research Interests: Systems Architecture, Information Systems, Process Control System


Dr. M. K Soni did his B.Sc (Engg.) in 1972 and M.Sc (Engg.) in 1975 from REC Kurukshetra (Now NIT Kurukshetra) and thereafter completed hid Ph.D from REC Kurukshetra (in collaboration with IIT Delhi) in 1988. He has a total 39 years of rich experience into Academics. His area of interest is microprocessor based control systems and digital system design. He has more than 100 research papers in the International and National Journals to his credit. Presently he is Pro Vice Chancellor at Manav Rachna International University Faridabad.

Author Articles
Design and Analysis of Tunnel FET for Low Power High Performance Applications

By Umesh Dutta M.K.Soni Manisha Pattanaik

DOI: https://doi.org/10.5815/ijmecs.2018.01.07, Pub. Date: 8 Jan. 2018

Tunnel FET is a promising device to replace MOSFET in low power high performance applications. This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs1-xSbx-InAs) based TFET device. Simulations are performed using TCAD tool and simulation results suggest that conventional DGTFET device has less on current and degraded subthreshold slope as compared to InAs and III-V semiconductor based TFET device. InAs based TFET device provides steep subthreshold slope of 61 mV/dec and off current of the order of nano-amperes at sub 1V operation thereby making it an ideal choice for low power high performance applications. The variation in the performance of the III-V HTFET device with the variation in the mole fraction is also studied in detail. Carefully choosing the mole fraction value in III-V semiconductor based HTFET device can lead to better device performance.

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Dynamic and Real-time Sleep Schedule Protocols for Energy Efficiency in WSNs

By Kaebeh Yaeghoobi S.B. M.K.Soni S.S. Tyagi

DOI: https://doi.org/10.5815/ijcnis.2016.01.02, Pub. Date: 8 Jan. 2016

Wireless Sensor Networks are emerging technologies that are diverse on energy consumption from different aspects. In the task mode, energy consumption of sensor nodes is categorized in, data packet transmitting, data processing and idle mode. Fundamentally, higher power is required and utilized at the time of data trans-receive as comparing to idle mode. However, power consumption of sensor in idle mode is necessarily important. To conserve energy, the network must provide quality of service sleep schedule, and use a mechanism to turn off the radio receiver periodically in coordinating method. Moreover, through dynamically round task management of sensors, significant energy saving can be achieved. Based on tasks and sleep schedules, nodes can form their clusters. It is necessary for real-time wireless applications to cogitate data transmit at the actual and response time based on the queries or tasks. This paper proposes Dynamic Immediate Data Report (DIDR) for real-time communication to schedule sleep mode of sensors in the network. Furthermore, to minimize the network energy consumption, Dynamic Schedule Data Report (DSDR) method is proposed. This method shows its efficiency by reducing the active time of nodes in the network. The performance analysis of the proposed works, illustrate effectively more energy efficiency as compared to existing methods.

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Role of Mobile Agents in the Layered Architecture of Mobile Ad-hoc Networks

By Bindiya Bhatia M.K.Soni Parul Tomar

DOI: https://doi.org/10.5815/ijcnis.2015.11.04, Pub. Date: 8 Oct. 2015

In today’s world mobile agents and mobile ad-hoc networks are the two technologies that are contributing towards better connectivity and communicability. When the two technologies used jointly, the interest is increased. Due to the properties like self-configuration and infrastructure-less, the mobile ad-hoc networks provide various remarkable features. But the various challenges are also associated with mobile ad-hoc networks like dynamic topology, mobility, energy constraint etc. Mobile agent provides solution to these challenges. A mobile agent is a new way of computer interactions and provides better options for the developers to create applications based on connectivity. Mobile agents move around the ad-hoc networks in a different and better way than the other widespread client server architecture based applications. Due to their mobility and autonomy these agents can perform various functions in mobile ad-hoc networks like topology discovery, routing, key management, congestion control etc. The paper reviews the role of the mobile agents in the mobile ad-hoc networks, and emphasizes its application on the various layers of a layered architecture of mobile ad-hoc networks and concludes its merits as compared to other conventional approaches.

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Analysis of Rotman Lens Antenna for Different Substrates for Circular Contour

By Shruti Vashist M.K.Soni P.K.Singhal

DOI: https://doi.org/10.5815/ijigsp.2014.08.08, Pub. Date: 8 Jul. 2014

This paper presents a trifocal Rotman lens design approach. The effect due to change of substrate on the circular contour is observed. The shape of the beam contour is taken as circular. Different substrates can be used for the fabrication of the lens. Three different materials have been used to fabricate the lens antenna .A three beam prototype feeding five element antenna array working in ISM band has been simulated using RLD1.7.Effects on the performance of the antenna is observed.

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Simulation and Optimization of VHDL code for FPGA-Based Design using Simulink

By Naresh Grover M.K.Soni

DOI: https://doi.org/10.5815/ijieeb.2014.03.04, Pub. Date: 8 Jun. 2014

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA's have become increasingly important and have found their way into all kind of digital system design This paper presents a novel, easy and efficient approach of implementation and verification of VHDL code using Simulink and then to regenerate the optimized VHDL code again using Simulink. The VHDL code written for the complicated digital design of 32-bit floating point arithmetic unit has been synthesized on Xilinx, verified and simulated on Simulink. The same VHDL code in Modelsim was optimized using this approach and the optimized code so generated by Simulinkhas also been synthesized to compare the results. Power dissipations for both synthesized designs using Xilinx Power Estimator were also extracted for comparison.

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Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

By Naresh Grover M.K.Soni

DOI: https://doi.org/10.5815/ijieeb.2014.01.01, Pub. Date: 8 Feb. 2014

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.

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A Novel Routing Scheme for Mobile Ad Hoc Network

By Prem Chand M.K.Soni

DOI: https://doi.org/10.5815/ijcnis.2013.04.03, Pub. Date: 8 Apr. 2013

Mobile Ad hoc Network (MANET) is a collection of mobile users without any support of fixed infrastructure. The nodes in these networks have several constraints such as transmission power, bandwidth and processing capability. In addition to it an important parameter of interest is the residual battery power of the nodes. Conventional routing schemes do not take this aspect into consideration. Therefore this paper proposes a routing strategy that takes this aspect into consideration by modifying the Route Request (RREQ) packet of the Ad hoc On demand Distance Vector (AODV) routing protocol. The protocol chooses a threshold below which a node is not allowed to relay data/control packets. The results show a remarkable improvement in the value of Packet Delivery Ratio (PDR), throughput and at the same time the network lifetime is not affected.

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Reduction of Power Consumption in FPGAs - An Overview

By Naresh Grover M.K.Soni

DOI: https://doi.org/10.5815/ijieeb.2012.05.07, Pub. Date: 8 Oct. 2012

Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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