Galua Field Multipliers Core Generator

Full Text (PDF, 869KB), PP.1-14

Views: 0 Downloads: 0


I. M. Zholubak ,* V. S. Hlukhov

1. Lviv Polytechnic National University, Computer Engineering Department, Stepana Bandery 12, Lviv, Ukraine

* Corresponding author.


Received: 28 Jul. 2022 / Revised: 12 Nov. 2022 / Accepted: 1 Apr. 2023 / Published: 8 Jun. 2023

Index Terms

Modified Guild cell (MGC), Galois fields (GF), Boolean functions, Galua field multiplier generator, field programmable gate array (FPGA)


An important part of based on elliptical curves cryptographic data protection is multipliers of Galois fields. For based on elliptical curves digital signatures, not only prime but also extended Galois fields GF(pm) are used. The article provides a theoretical justification for the use of extended Galois fields GF(dm) with characteristics d > 2, and a criterion for determining the best field is presented. With the use of the proposed criterion, the best fields, which are advisable to use in data protection, are determined.
Cores (VHDL descriptions of digital units) are considered as structural part of based on FPGA devices. In the article methods for cryptoprocessors cores creating were analyzed. The article describes the generator of VHDL descriptions of extended Galois field multipliers with big characteristic (up to 2998). The use of mathematical packages for calculations to improve the quality of information security is also considered.
The Galois field multipliers generator creates the VHDL description of multipliers schemes, describes connections of their parts and generates VHDL descriptions of these parts as result of Quine-McCluskey Boolean functions minimization method. However, the execution time of the algorithm increases with increasing amount of input data. Accordingly, generating field multipliers with large characteristic can take frерom a few seconds to several tens of seconds.
It's important to simplify the design and minimize logic gates number in a field programmable gate array (FPGA) because it will speed up the operation of multipliers. The generator creates multipliers according to the three variants.
The efficiency of using multipliers for fields with different characteristics was compared in article.
The expediency of using extended Galois fields GF(dm) with characteristics d > 2 in data protection tools is analyzed, a criterion for comparing data protection tools based on such Galois fields is determined, and the best fields according to the selected criterion when implemented according to a certain algorithm are determined.

Cite This Paper

I. M. Zholubak, V. S. Hlukhov, "Galua Field Multipliers Core Generator", International Journal of Computer Network and Information Security(IJCNIS), Vol.15, No.3, pp.1-14, 2023. DOI:10.5815/ijcnis.2023.03.01


[1]Quine, Willard Van Orman, "The Problem of Simplifying Truth Functions", The American Mathematical Monthly, Vol.59, No.8, pp. 521–531, 1952. DOI:10.2307/2308219. JSTOR 2308219
[2]Sudha Ellison, Mathe Lakshmi Boppana, “Bit-parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations”, Department of Electronics and Communicating Engineering, National Institute of Technology, Varangal, Telangana 506004, India, IET Journal IET Circuits Devices Syst., Vol. 12, Iss. 4, pp. 315-325, 2018. DOI:10.1049/iet-cds.2017.0426
[3]H. El-Razouk, "Input-Latency Free Versatile Bit-Serial GF(2m) Polynomial Basis Multiplication," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 5, pp. 589-602, May 2022, doi: 10.1109/TVLSI.2022.3155611.
[4]R. Bulat and M. R. Ogiela, "Personalized Cryptography Algorithms – A Comparison Between Classic and Cognitive Methods," 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S), 2022, pp. 43-44, doi: 10.1109/DSN-S54099.2022.00026.
[5]David Kohel, “Arithmetic statistics of Galois groups”, The open book series, 2019, V.1, pp. 353-374.
[6]M. A. Mehrabi, C. Doche and A. Jolfaei, "Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module," in IEEE Transactions on Computers, vol. 69, no. 11, pp. 1707-1718, 1 Nov. 2020, doi: 10.1109/TC.2020.3013266.
[7]X. Heng, J. Shen, N. Fan and W. Gao, "Fast Continuous Scalar Multiplication Algorithms on Twisted Edwards Elliptic Curve," 2022 International Conference on Networks, Communications and Information Technology (CNCIT), 2022, pp. 89-95, doi: 10.1109/CNCIT56797.2022.00022.
[8]Zholubak I., Hlukhov V., “Hardware costs of the Galois field GF(dm) with large base”, “Computer Systems and Networks”, № 881, Publishing House of Lviv Polytechnic National University, Lviv, pp. 41 – 47, 2017. DOI: csn2017. 881.041
[9]V. Hlukhov, A. Kostyk, I. Zholubak, M. Rahma. “Galois Fields Elements Processing Units for Cryptographic Data Protection in Cyber-Physical Systems”, Advances in Cyber-Physical Systems, Volume 2, Number 2, Lviv Polytechnic National University, pp. 47 – 53, 2017.
[10]Rodrigue Elias, Valerii Hlukhov, Mohammed Rahma, Ivan Zholubak, “FPGA cores for fast multiplicative inverse calculation in Galois Fields”, Electrotechnic and computer systems, Odessa, pp. 227-233, 2018. DOI:
[11]J. L. Imana, "LFSR-Based Bit-Serial GF(2m) GF(2m) Multipliers Using Irreducible Trinomials," in IEEE Transactions on Computers, vol. 70, no. 1, pp. 156-162, 1 Jan. 2021, doi: 10.1109/TC.2020.2980259.
[12]Hari Krishna Balupala, Kumar Rahul, Santosh Yachareni, “Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography”, IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), pp. 1-6, 2021. DOI: 10.1109/IEMTRONICS52119.2021.9422551
[13]Hariveer Inumarty, Mohamed Asan Basiri M., “Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations”, 24th International Symposium on VLSI Design and Test (VDAT), pp. 1-5, 2020. DOI: 10.1109/VDAT50263. 2020.9190485
[14]Iván Jirón, Ismael Soto, Sebastián Gutiérrez, Raúl Carrasco, “Reed-Solomon codes over Galois fields of characteristic 3 for a VLC channel”, South American Colloquium on Visible Light Communications (SACVC), pp. 1-5, 2020. DOI: 10.1109/ SACVLC50805.2020.9129896
[15]Fedir Geche, Oksana Mulesa, Veronika Voloshchuk, Anatoliy Batyuk, “Generalized Logical Neural Functions Over The Galois Field And Their Properties”, IEEE 14th International Conference on Computer Sciences and Information Technologies (CSIT), pp. 21-24, 2019. DOI: 10.1109/STC-CSIT.2019.8929867
[16]Sergei Shalagin, Vjachtslav Zakharov, “Implementing the Markov Probability Functions Based on a Set of Polynomials over Galois Field”, International Conference on Information Technology and Nanotechnology (ITNT), pp. 1-3, 2021. DOI: 10.1109/ITNT52450.2021.9649171
[17]J. Xie, C. -Y. Lee, P. K. Meher and Z. -H. Mao, "Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over GF(2m) Based on Reordered Normal Basis," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 9, pp. 2119-2130, Sept. 2019, doi: 10.1109/TVLSI.2019.2918836.
[18]Kashi Nath Datta, Sujoy Saha, “Binomial Galois Field Based Asynchronous Non-Adaptive Mode Energy Management System”, 11th International Conference on Communication Systems & Networks (COMSNETS), pp. 510-512, 2019. DOI: 10.1109/COMSNETS.2019.8711217
[19]Ju-Hwan Kim, Bo-Yeon Sim; Dong-Guk Han, “Optimized Power Consumption Model for Multiplication in Galois Field of AES”, International Conference on Platform Technology and Service (PlatCon), pp. 1-3, 2019. DOI: 10.1109/PlatCon.2019.8669430
[20]Ilya V. Chugunkov, Lilia D. Gatilova, Michael A. Ivanov, Bogdana V. Kliuchnikova, Alexander A. Kozlov, Evgeniy A. Salikov, “Computing in Finite Fields”, Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus), pp. 273-276, 2022. DOI: 10.1109/ElConRus54750.2022.9755751
[21]Rahma, M., Zholubak, I., Hlukhov, V., “Devices for multiplicative inverse calculation in the binary Galois fields”, Proceedings of 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies, DESSERT 2018, pp. 261–264, 2018. DOI: 10.1109/DESERT.2018.8409141
[22]Krishn Kumar Gupt, Meghana Kshirsagar, Joseph P. Sullivan, Conor Ryan, “Automatic Test Case Generation for Vulnerability Analysis of Galois Field Arithmetic Circuits”, IEEE 5th International Conference on Cryptography, Security and Privacy (CSP), pp. 32-37, 2021. DOI: 10.1109/CSP51677.2021.9357567
[23]Sergei Shalagin, Vjacheslav Zakharov, “Distributed Nonlinear-Polynomial Computing Based on a Group of Polynomials over a Galois Field in the FPGA Architecture”, IEEE 15th International Conference on Application of Information and Communication Technologies (AICT), pp. 1-4, 2021. DOI: 10.1109/AICT52784.2021.9620296
[24]H. K. Balupala, K. Rahul and S. Yachareni, "Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography," 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), 2021, pp. 1-6, doi: 10.1109/IEMTRONICS52119.2021.9422551.
[25]Rodriges Elias, Hlukhov V., Rahma M., Zholubak I., “Concurrent error detaction of devices for extended galois fields elements processing”, “Computer Systems and Networks”, № 905, Publishing House of Lviv Polytechnic National University, Lviv, pp. 64 – 72, 2018. DOI:
[26]DSTU 4145-2002 “Cryptographic protection of information. A digital signature based on elliptic curves”.
[27]Rodrigue Elias, Valerii Hlukhov, Mohammed Rahma, Ivan Zholubak, “FPGA cores for fast multiplicative inverse calculation in Galois Fields”, Electrotechnic and computer systems, Odessa, pp. 227-233, 2018. DOI:
[28]Melnyk A.O., Melnyk V.A., “Personal supercomputers”, Publishing House of the National University "Lviv Polytechnic", Lviv, 2012. - 600 pp.
[29]Sharma, A. Singh and A. Kumar, "Encryption and Decryption of Marker Based 3-Dimensional Augmented Reality Image Using Modified Hill Cipher Technique for Secure Transfer," 2022 IEEE 2nd International Conference on Computer Communication and Artificial Intelligence (CCAI), 2022, pp. 155-159, doi: 10.1109/CCAI55564.2022.9807727.
[30]Jiri Gaisler, "A structured VHDL Design Method", Retrieved 15 November 2017.
[31]L. Conway, "Reminiscences of the VLSI Revolution". Accessed 14, November 2019.
[32]H. S. Choo et al., "Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level," 2019 IEEE 28th Asian Test Symposium (ATS), 2019, pp. 98-980, doi: 10.1109/ATS47505.2019.00018.
[33]H. -G. Vu, N. -D. Bui, A. -T. Nguyen and ThanhBangLe, "Performance Evaluation of Quine-McCluskey Method on Multi-core CPU," 2021 8th NAFOSTED Conference on Information and Computer Science (NICS), 2021, pp. 60-64, doi: 10.1109/NICS54270.2021.9701506.
[34]P. Bhowmik, J. Hossain Pantho, J. Mandebi Mbongue and C. Bobda, "ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA," 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021, pp. 176-180, doi: 10.1109/FCCM51124.2021.00028.