Gaurav Jitendra Shahane

Work place: Department of Manufacturing Engineering and Industrial Management, School of Engineering and Technology, COEP Technological University, Chhatrapati Shivaji Maharaj Nagar, Pune: 411005, Maharashtra State, India

E-mail: gauravshahane21@gmail.com

Website: https://orcid.org/0009-0006-0075-4883

Research Interests:

Biography

Gaurav Jitendra Shahane is currently pursuing M.Tech. in Mechatronics at COEP Technological University, Pune. He obtained his B.E. in Mechanical Engineering from Padma Bhushan Vasantdada Patil Institute of Technology (PVPIT), Pune in 2024, affiliated with Savitribai Phule Pune University (SPPU). He has 2 years of industrial experience prior to his postgraduate studies

Author Articles
Self-Evolving Digital Twins for Industry 5.0: Autonomous Model-Plant Mismatch Correction and Human Centric Cognitive Integration in Cyber Physical System

By Gaurav Jitendra Shahane Sudhir Madhav Patil Hrishikesh Kishor Jadhav

DOI: https://doi.org/10.5815/ijem.2026.05.02, Pub. Date: 8 Oct. 2026

Industry 5.0 does not extend Industry 4.0; rather, it demands something structurally different. Monitoring and prediction are no longer sufficient. Modern production environments require Digital Twin (DT) architectures that correct themselves autonomously and treat operator expertise as a formal computational input. Two gaps in the current literature block this transition. The first is the absence of autonomous Model-Plant Mismatch (MPM) correction. Every reviewed DT framework retains at least one human dependency, such as scheduled re-identification, manual labeling, or engineer approval before changes are committed. This holds across 67 publications covering manufacturing robotics, Computer Numerical Control (CNC) machining, predictive maintenance, and process control. The second gap is architectural. Every reviewed DT interface pushes information toward the operator, but none route operator knowledge back into the computational model as a structured input. Two integrated frameworks address these gaps. The Adaptive Self-Evolving Digital Twin (ASEDT) closes Gap 1 through the Real-Time Anomaly Detection Engine (RADE) anomaly detection, Online Parameter Estimation Module (OPEM) Bayesian parameter estimation, Structural Model Adaptation Layer (SMAL) meta-learning structural adaptation and Evolution Audit and Rollback Controller- (EARC) governed rollback validation. The Human Centric Cognitive Synchronization (HCCS) framework closes Gap 2 through Operator Intent Capture Layer (OICL) observation classification, Explainable State Presentation Layer (XSPL) expertise stratified presentation and Shared Mental Model Alignment Engine (SMMAE) continuous Mental Model Distance Metric (MMDM) computation. Both are coupled through the Triadic Feedback Architecture (TFA). ASEDT is validated via Software-in-the-Loop (SIL) testing on a Siemens NX MCD (Mechatronics Concept Designer) four corner punching machine at 100 Hz. Across 12 MPM scenarios it achieves a 62.6-94.1% Root Mean Square Error (RMSE) reduction, a 30 ms detection latency, parametric convergence within 4.7-11.9 minutes and zero manual interventions. HCCS empirical validation through a planned longitudinal study (N = 40, counterbalanced, with Tobii eye tracking) is described in Section 5.6.

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