S. Venkateswarlu

Work place: RGM College of Engineering & Technology, (Autonomous), JNT University-ATP, Nandyal, Andhra Pradesh-518501, India



Research Interests: Computational Science and Engineering, Computational Mathematics, Computer systems and computational processes, Logic Calculi, Computational Complexity Theory, Logic Circuit Theory


S. Venkateswarlu: Professor in the department of Mathematics at Rajeev Gandhi Memorial College of Engg & Technology, Nandyal, Andhra Pradesh-India. He received Ph.D degree from S. K University, Anantapur.

His area of interest includes FEM, FDM, Fuzzy logic, and computational methods using Matlab.

Author Articles
A Comparative Performance Analysis of Low Power Bypassing Array Multipliers

By Nirlakalla Ravi S. Venkateswarlu T. Jayachandra Prasad Thota Subba Rao

DOI: https://doi.org/10.5815/ijitcs.2013.08.04, Pub. Date: 8 Jul. 2013

Low power design of VLSI circuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP). Multiplier has an important role in the DSPs. Without degrading the performance of the processor, low power parallel multipliers are needed to be design. Bypassing is the widely used technique in the DSPs when the input operand of the multiplier is zero. A Row based Bypassing Multiplier with compressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed. The proposed bypassing multiplier with compressor shows high performance and energy efficiency than Kuo multiplier with Carry Save Adder (CSA) at the final RCA.

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