Abhishek Nag

Work place: Department of Electronics and Communication Engineering, NIT Agartala, Jirania, Tripura, India 799046

E-mail: abhi14379@gmail.com


Research Interests: Engineering, Computational Engineering, Computational Science and Engineering


Abhishek Nag was born in Agartala, India, in 1989. He received his B.Tech Degree from Dr. MGR Educational and Research Institute in 2011 and his M.Tech Degree from National Institute of Technology (NIT) Agartala in 2013. He is currently pursuing the Ph.D. degree from National Institute of Technology Agartala, India, to do research on low power VLSI Design with special reference to power and clock gating techniques in FPGA as well as ASIC.

Author Articles
A CLB Priority based Power Gating Technique in Field Programmable Gate Arrays

By Abhishek Nag Sambhu Nath Pradhan

DOI: https://doi.org/10.5815/ijigsp.2018.05.02, Pub. Date: 8 May 2018

In this work, an autonomous technique of power gating is introduced at coarse level in Field Programmable Gate Array (FPGA) architecture to minimize leakage power. One of the major disadvantages of FPGA is the unnecessary power dissipation associated with the unused logic/inactive blocks. These inactive blocks in a FPGA are automatically cut-off from the power supply in this approach, based on a CLB priority algorithm. Our method focuses on introducing gating into both the logic blocks and routing resources of an FPGA at the same time, contrary to previous approaches. The proposed technique divides the FPGA fabric into clusters of CLBs and associated routing resources and introduces power gating separately for each cluster during runtime. The FPGA prototype has been developed in Cadence virtuoso spectrum at 45 nm technology and the layout of the proposed power gated FPGA is developed also. Simulation has been carried out for a ‘4 CLB’ prototype and results in a maximum of 55 % power reduction. The area overhead is 1.85 % for the ‘4 CLB’ FPGA prototype and tends to reduce with the increase in number of CLBs. The area overhead of a ‘128 CLB’ FPGA prototype is only 0.058 %, considering 4 sleep transistors. As an extension to the proposed gating in ‘4 CLB’ prototype, two techniques for an ‘8 CLB’ prototype are also evaluated in this paper, each having its own advantages. Due to the wake up time associated with power gated blocks, delay tends to increase. The wake-up time however, reduces with the increase in sleep transistor width.

[...] Read more.
Other Articles