S. M. Shamsul Alam

Work place: Electronics and Communication Engineering Discipline, Khulna University, Khulna 9208, Bangladesh

E-mail: alam_ece@yahoo.com

Website: https://orcid.org/0000-0003-3376-5950

Research Interests: Processor Design


S. M. Shamsul Alam received the B.Sc. (Engg.) degree in Electronics and Communication Engineering from Khulna University, Khulna, Bangladesh in 2004 and M. Engg. degree from the Department of Information and Communication Engineering Chosun University, Gwnagju, Korea, under the Global IT, NIPA scholarship program in2013. From 2011 to 2013, he was working as a Research Assistant with the Department of Information and Communication Engineering, Chosun University, Gwangju, Korea. Currently, he is with the Electronics and Communication Engineering (ECE) Discipline, Khulna University, Khulna, Bangladesh and is serving as a Faculty Member in the ECE Discipline. His research interests include Chip Design and Application Specific Processor Design for communication systems.

Author Articles
Design and Implementation of Multi Player Pong Game using Altera DE2 Board

By Tonmoy Saha A K Tasfique Ahmed S. M. Shamsul Alam

DOI: https://doi.org/10.5815/ijisa.2023.06.03, Pub. Date: 8 Dec. 2023

Pong game is a simple but entertaining game of logic control. This research paper presents the design and implementation of an FPGA-based Pong game that runs on an Altera DE2 board using Verilog HDL. This article explains the VGA controller, object creation and animation, and text subsystem and of course how to link them all together to build a functioning circuit. There is an interesting multi-player mode and single-player mode feature in this design scheme. This game's multiplayer mode features both real-time and automatic players to create a competitive atmosphere. This design method followed less complicated, fastest processing, and utilized memory requirements and logic elements. The single-player mode uses 1.3% of total logic elements, the two-player mode uses 1.32%, and automatic player vs. real player uses 1.456% of total logic elements which is very small compared to the other gaming schemes and it reduces the processing time that is cost-effective for universal use. All the modules are designed by using Verilog HDL. The synthesis is done with the help of Altera DE2 FPGA. Functional simulation and synthesis prove that the design is universally usable and combines different modules in one module that presents sound entertainment and extends the electronics application-based work in the future.

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Performance Comparison of OFDM, FBMC, and UFMC for Identifying the Optimal Solution for 5G Communications

By Sourav Debnath Samin Ahmed S. M. Shamsul Alam

DOI: https://doi.org/10.5815/ijwmt.2023.05.01, Pub. Date: 8 Oct. 2023

The fifth generation (5G) wireless technology has a significant impact on individuals' lives and work, and this impact is expected to increase in the future. The Orthogonal Frequency Division Multiplexing (OFDM) method, which is currently used in fourth generation (4G) technology, has limitations in meeting certain criteria such as data rates and speed for the latest technology due to issues such as sideband leakages, high Peak-to-Average Power Ratio (PAPR), and poor spectrum utilization. Additionally, the increasing demand for Internet of Things (IoT) and user-centric processing makes the OFDM method impractical. As a result, alternative technologies are being explored to meet these needs. Filter Bank Multicarrier (FBMC) and Universal Filtered Multicarrier (UFMC) are potential candidates for 5G technology. This paper focuses on the evolution of FBMC from OFDM, and then compares the performance of FBMC and UFMC by analyzing various modulation schemes such as Quadrature Amplitude Modulation (QAM), Phase Shift Keying (PSK), PAPR, and Bit Error Rate (BER) through Additive White Gaussian Noise (AWGN) and Rayleigh fading channels. A theoretical BER model is also established to validate the simulated BER results. In this paper BER is analyzed in terms mathematical and simulation based approaches. To validate this simulation based method, it can be compared with the theoretical BER results to verify the accuracy of this simulation. Result portays that, the theoretical results and the simulated results are quite close through the Additive White Gaussian Noise (AWGN) channel.

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Static Timing Analysis of Different SRAM Controllers

By Jabin Sultana S. M. Shamsul Alam

DOI: https://doi.org/10.5815/ijisa.2023.03.03, Pub. Date: 8 Jun. 2023

Timing-critical path analysis is one of the most significant terms for the VLSI designer. For the formal verification of any kinds of digital chip, static timing analysis (STA) plays a vital role to check the potentiality and viability of the design procedures. This indicates the timing status between setup and holding times required with respect to the active edge of the clock. STA can also be used to identify time sensitive paths, simulate path delays, and assess Register transfer level (RTL) dependability. Four types of Static Random Access Memory (SRAM) controllers in this paper are used to handle with the complexities of digital circuit timing analysis at the logic level. Different STA parameters such as slack, clock skew, data latency, and multiple clock frequencies are investigated here in their node-to-node path analysis for diverse SRAM controllers. Using phase lock loop (ALTPLL), single clock and dual clock are used to get the response of these controllers. For four SRAM controllers, the timing analysis shows that no data violation exists for single and dual clock with 50 MHz and 100 MHz frequencies. Result also shows that the slack for 100MHz is greater than that of 50MHz. Moreover, the clock skew value in our proposed design is lower than in the other three controllers because number of paths, number of states are reduced, and the slack value is higher than in 1st and 2nd controllers. In timing path analysis, slack time determines that the design is working at the desired frequency. Although 100MHz is faster than 50MHz, our proposed SRAM controller meets the timing requirements for 100MHz including the reduction of node to node data delay. Due to this reason, the proposed controller performs well compared to others in terms slack and clock skew.

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Performance Analysis of LT Codec Architecture Using Different Processor Templates

By S. M. Shamsul Alam

DOI: https://doi.org/10.5815/ijitcs.2019.08.06, Pub. Date: 8 Aug. 2019

Luby Transform (LT) code plays a vital role in binary erasure channel. This paper portrays the design techniques for implementation of LT codec using application specific instruction set processor (ASIP) design tools. In ASIP design, a common approach to increase the performance of processors is to boost the number of concurrent operations. Therefore, optimizations like strategy of input design, processor and compiler architecture are very useful phenomenon to enhance the performance of the application specific processor. Using Tensilica and OpenRISC processor design tools, this paper shows the response of LT codec architectures in terms of cycle counts and simulating time. Result shows that, the simulation speed of Tensilica is very high compared to the OpenRisc tool. Among different configurations of Tensilica tool, proposed ConnXD2 design took 1 M cycles per second and 135.66 ms to execute LT codec processor and XRC_D2MR configuration consumed only 9 iterations for successful decoding of LT encoded signal. Besides this, OpenRisc tool took 142K cycles and 6ms for executing LT encoder.

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