Hemalatha K N

Work place: Dr. Ambedkar Institute of Technology, Visveswaraya Technological University

E-mail: knhemalatha@gmail.com


Research Interests: Embedded System, Systems Architecture


Mrs. Hemalatha K N received her B. E in the year 2003, and M. Tech in 2010 from VTU. Currently working as Assistant Professor in the Department of Electronics & Communication at Dr. Ambedkar Institute of Technology. Area of Interest is VLSI & Embedded systems, and Digital design.

Author Articles
Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic

By Hemalatha K N Sangeetha B G

DOI: https://doi.org/10.5815/ijem.2022.04.03, Pub. Date: 8 Aug. 2022

Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology. When building quantum computers, for example, the use of reversible logic is unavoidable. The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit. The multiplication operation is regarded as one of the most crucial in the ALU unit. In this study, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits. The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic. The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.

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