Work place: S.M.K Fomra Institute of technology, Chennai

E-mail: salem_farh@yahoo.com


Research Interests: Engineering


K.Kalaikaviya received her B.E. degree in Electronics and communication engineering at Periyar Maniammai college of technology for women under Anna university, Tiruchirapalli. Currently pursuing her M.Tech Degree in S.M.K Fomra institute of technology.Area of interest is digital electronics, vlsi design,Testing of vlsi.

Author Articles
Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder

By K.KalaiKaviya D.P.Balasubramanian S.Tamilselvan

DOI: https://doi.org/10.5815/ijem.2013.02.03, Pub. Date: 16 Sep. 2013

Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexities of algorithms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array multiplier to achieve high execution speed or to meet the performance demands. A typical implementation of such an array multiplier is Braun design. Braun multiplier is a type of parallel array multiplier. The architecture of Braun multiplier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. In this research work, a new design of Braun Multiplier is proposed and this proposed design of multiplier uses a very fast parallel prefix adder (Brent kung Adder) in place of Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the area and delay due to Ripple Carry Adder and performing faster multiplication of two binary numbers. The design is implemented using Microwind1, digital schematics (DSCH)

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