Work place: Department of ECE, M.V.J College of Engineering, Bangalore, India



Research Interests: Computer systems and computational processes, Systems Architecture, Data Structures and Algorithms


M.Brindha completed Bachelor in Engineering (2004). Master of Engineering from Anna University, Chennai (2006). . She is currently an Associate Professor in the Department of ECE, M.V.J. College of Engineering, Bangalore, India She has published many journals and attended many Conferences in National and International Level. Her research areas are embedded Systems, FPGA Implementation and Algorithms. email:

Author Articles
High Performance Network Security Using NIDS Approach

By Sutapa Sarkar Brindha.M

DOI:, Pub. Date: 8 Jun. 2014

Ever increasing demand of good quality communication relies heavily on Network Intrusion Detection System (NIDS). Intrusion detection for network security demands high performance. This paper gives a description of the available approaches for a network intrusion detection system in both software and hardware implementation. This paper gives a description of the structure of Snort rule set which is a very popular software signature and anomaly based Intrusion Detection and prevention system. This paper also discusses the merit of FPGA devices to be used in network intrusion detection system implementation and the approaches used in hardware implementation of NIDS.

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Hardware Implementation of Elliptic Curve Cryptography over Binary Field

By Sandeep S.V Hameem Shanavas .I Nallusamy.V Brindha.M

DOI:, Pub. Date: 8 Mar. 2012

This paper presents high-performance Elliptic Curve Cryptography (ECC) architecture over binary field, based on the Montgomery scalar multiplication algorithm. The word-serial finite field arithmetic unit (AU) is proposed with the optimized operation scheduling and bit-parallel modular reduction. With a dedicated squarer, the 163-bit point scalar multiplication with coordinate conversion can be done in 20.9μs by the design of one AU, and can be further improved to 11.1μs by the one of three AUs, both using 0.13μm CMOS technology. The comparison with other ECC designs justifies the effectiveness of the proposed architecture in terms of performance and area-time efficiency.

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