Bahman Rashidi

Work place: School of Computer Engineering, Iran University of Science and Technology, Iran, Tehran



Research Interests: Database Management System, Distributed Computing, Computer Networks, Computer Vision


Bahman Rashidi received his B.SC. Degree in Computer Engineering from the University of Isfahan, IRAN, in 2009 and he is now M.SC. In the Iran University of Science and Technology, Tehran, IRAN, respectively. He has published seven refereed conference and journal papers. His research interests are mostly about Distributed Systems, Cloud Computing, Communication Protocols and Computer Software.

Author Articles
A Survey on Interoperability in the Cloud Computing Environments

By Bahman Rashidi Mohsen Sharifi Talieh Jafari

DOI:, Pub. Date: 8 Jun. 2013

In the recent years, Cloud Computing has been one of the top ten new technologies which provides various services such as software, platform and infrastructure for internet users. The Cloud Computing is a promising IT paradigm which enables the Internet evolution into a global market of collaborating services. In order to provide better services for cloud customers, cloud providers need services that are in cooperation with other services. Therefore, Cloud Computing semantic interoperability plays a key role in Cloud Computing services. In this paper, we address interoperability issues in Cloud Computing environments. After a description of Cloud Computing interoperability from different aspects and references, we describe two architectures of cloud service interoperability. Architecturally, we classify existing interoperability challenges and we describe them. Moreover, we use these aspects to discuss and compare several interoperability approaches.

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FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal

By Bahram Rashidi Bahman Rashidi

DOI:, Pub. Date: 8 Feb. 2013

This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of information between combinatorial blocks without a global clock signal. The self-timed architectures are asynchronous circuits which perform their function based on local synchronization signals called hand shake, independently from the other modules. This new architecture reduced spikes on current consumption and only parts with valid data are working, and also this design does not need any clock pulse. A combinational logic based Rijndael S-Box implementation for the Substitution Byte transformation in AES is proposed, its low area occupancy and high throughput therefore proposed digital design leads to reduction in power consumption. Mix-columns transformation is implemented only based on multiply-by-2 and multiply-by-3 modules with combinational logic. The proposed novel asynchronous self-timed AES algorithm is modeled and verified using FPGA and simulation results from encryption of sound signals is presented, until original characteristics are preserved anymore and have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. The achieved power consumption is 283 mW in clock frequency of 100 MHz.

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Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA

By Bahram Rashidi Bahman Rashidi

DOI:, Pub. Date: 8 Jan. 2013

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the AES cryptographic module thus we implement its mathematic equations based on optimized and combinational logic circuits until dynamic power consumption reduced. The complete data path of the S-box algorithm is simulated as a net list of AND, OR, NOT and XOR logic gates, also for increase in speed and maximum operation frequency used 4-stage pipeline in proposed method. The proposed implemented combinational logic based S-box have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. Power is analized using Xilinx XPower analyzer and achieved power consumption is 29 mW in clock frequency of 100 MHz. The results from the Place and Route report indicate that maximum clock frequency is 209.617 MHz.

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Implementation of a High Speed Technique for Character Segmentation of License Plate Based on Thresholding Algorithm

By Bahram Rashidi Bahman Rashidi

DOI:, Pub. Date: 8 Nov. 2012

This paper presents, complete step by step description design and implementation of a high speed technique for character segmentation of license plate based on thresholding algorithm. Because of vertical edges in the plate, fast Sobel edge detection has been used for extracting location of license plate, after stage edge detection the image is segmented by thresholding algorithm and the color of characters is changed to white and the color of background is black. Then, boundary’s pixels of license plate are scanned and their color is changed to black pixels. Afterward the image is scanned vertically and if the number of black pixels in a column is equal to the width of plate or a little few, then the pixels of that column is changed to white pixel, until create white columns between characters, in continue we change pixels around license plate to white pixels. Finally characters are segmented cleanly. We test proposed character segmentation algorithm for stage recognition of number by code that we design. Results of experimentation on different images demonstrate ability of proposed algorithm. The accuracy of proposed character segmentation is 99% and average time of character segmentation is 15ms with thresholding algorithm code and 0.7ms only segmentation character code that is very small in comparison with other algorithms.

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