Wireless Sensor Networks (WSNs) play a crucial role in applications such as remote monitoring, surveillance, and the Internet of Things (IoT). Addressing the challenge of energy consumption is paramount in WSN design due to the finite nature of energy resources. In cluster-based WSNs, cluster heads (CH) perform vital tasks like data collection, data aggregation, and exchange with the base station. Therefore, achieving efficient load balancing for CHs is crucial for maximizing network longevity. Previous studies have considered load balancing with optimal CH selection, but the issue of data redundancy is not addressed. Data redundancy in processing and transmitting information to analysis centres significantly depletes sensor resources like (energy, bandwidth and such). This paper proposes a novel energy-efficient data aggregation approach with data compression termed C-EWaOA that is (Compression based Enhanced Walrus Optimization with a cognitive factor). The non-negative matrix factorization (NMF) is used to compress the data and remove the redundant information. This way, the proposed data aggregation scheme reduces packet delivery Ratio, resulting in low data-rate communication. Simultaneously, data compression minimizes redundancy in aggregated data at CH, reducing resource consumption, leading to energy cost savings, and facilitating the transmission of a compact data stream in the communication bandwidth. The proposed approach shows a 0.606% improvement in network lifetime compared to the approach without compression and 68.01% of energy consumption. Notably, it achieves a reduction of 78.57% in packet loss ratio compared to the state-of-the-art FEEC-IIR model. Thus, the proposed approach shows remarkable improvement in energy-efficient data aggregation with data compression in WSN showcasing its prominence in IoT-based applications.

Digital electronics is the backbone of current technology, play a pivotal role in the growth of humanity. Digital memory is part of digital electronics consists flip-flops building blocks designed by using logical NAND and NOR gates. Validation of storing information in form of bits can be understood from analysis of working of flip-flops. In the present investigation, VI Model of the different flip flops in LabVIEW has been realized and simulation implementation of flip flops is utilized to analyze the functioning of memory elements. The characteristics table of all kind of flip flop is verified using VI Models. Moreover, different flip-flops are also realized in MATLAB using Simulink. In the phase of digital and internet, this student -centric learning of existing theory of flip-flops can easily understand using simulation environment.