Rajendra Bahadur Singh

Work place: School of Information & Communication Technology, Gautam Buddha University, Greater Noida, India

E-mail: rbs2006vlsi@gmail.com


Research Interests:


Rajendra Bahadur Singh has completed B.Tech, M.Tech and Ph.D. He is working as Research/ Faculty Associate in the department of Electronics & Communication Engineering, Gautam Buddha University, India. His areas of interest are VLSI design, IC physical design using soft computing, Micro-electronics. He has supervised more than 40 M.Tech dissertations.

Author Articles
IC Floorplanning Optimization using Simulated Annealing with Order-based Representation

By Rajendra Bahadur Singh Anurag Singh Baghel

DOI: https://doi.org/10.5815/ijisa.2021.02.05, Pub. Date: 8 Apr. 2021

Integrated Circuits (IC) floorplanning is an important step in the integrated circuit physical design; it influences the area, wire-length, delay etc of an IC. In this paper, Order Based (OB) representation has been proposed for fixed outline floorplan with Simulated Annealing (SA) algorithm. To optimize the IC floorplan, two physical quantities have been considered such as area, and wire-length for hard IP modules. Optimization of the IC floorplan works in two phases. In the first phase, floorplans are constructed by proposed representation without any overlapping among the modules. In the second phase, Simulated Annealing algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire-length. The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that our proposed representation with SA algorithm performs better for area and wire-length optimization than the other methods. The results are compared with the solutions derived from other algorithms. The significance of this research work is improvement in optimized area and wire-length for modern IC.

[...] Read more.
Other Articles