Neuromorphic RISC-V Systems for Bio-inspired Computing Applications

PDF (1521KB), PP.130-149

Views: 0 Downloads: 0

Author(s)

Yamini Devi Ykuntam 1,* M. V. Nageswara Rao 2 Leela Kumari. B. 3

1. ECE, Jawaharlal Nehru Technological University (JNTU), Kakinada, India

2. ECE, GMR Institute of Technology, India

3. ECE, UCEK, JNTUK, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijcnis.2026.04.07

Received: 25 Jan. 2025 / Revised: 20 May 2025 / Accepted: 2 Sep. 2025 / Published: 8 Aug. 2026

Index Terms

Neuromorphic Computing, Latency, Power Efficiency, Spiking Neural Networks, Ant Colony Optimization, RISC-V Architecture

Abstract

Neuromorphic computing is a paradigm based on the computational mechanisms of the human brain and has received considerable attention as a real-time technique with low energy requirements. Present systems, however, are limited in their ability to scale traditional processors to a neuromorphic architecture, leading to issues with latency, power consumption, and smooth data flow. To address these problems, this paper proposes the ACORISC-VbSNN framework, comprising a modular RISC-V architecture, Spiking Neural Networks (SNNs), and Ant Colony Optimization (ACO). The system uses a shared-memory architecture to maximize communication between traditional and neuromorphic processors, ensuring data is managed effectively. The postulated framework processes the sensory data by pre-processing and encoding them using rate coding, and dynamically optimizing memory access. SNNs are also used to process spike trains in real-time, whereas ACO is used to determine the best data paths to minimize bottlenecks. Experimental analysis shows that the system performs better, with ultra-low power consumption of 0.0095 mW, very low latency of 0.000544 seconds, and 99.2 percent accuracy. These findings indicate that the ACORISC-VbSNN model has the potential to advance the field of bio-inspired computing, providing a highly accurate, energy-efficient, and low-latency system for real-world use.

Cite This Paper

Yamini Devi Ykuntam, M. V. Nageswara Rao, Leela Kumari. B., "Neuromorphic RISC-V Systems for Bio-inspired Computing Applications", International Journal of Computer Network and Information Security(IJCNIS), Vol.18, No.4, pp. 130-149, 2026. DOI:10.5815/ijcnis.2026.04.07

Reference

[1]Z. Dong, X. Ji, C.S. Lai and D. Qi, “Design and implementation of a flexible neuromorphic computing system for affective communication via memristive circuits,” IEEE Communications Magazine, Vol. 61 No. 1, pp. 74-80, 2022.
[2]V.N. Balaji, P.B. Srinivas and M.K. Singh, “Neuromorphic advancements architecture design and its implementations technique,” Materials Today: Proceedings, Vol. 51, pp. 850-853, 2022.
[3]C. Frenkel, D. Bol and G. Indiveri, “Bottom-up and top-down approaches for the design of neuromorphic processing systems: tradeoffs and synergies between natural and artificial intelligence,” Proceedings of the IEEE Vol. 111, No. 6, pp. 623-652, 2023. 
[4]P. Quibuyen, T. Jiao and H.Y. Wong, “A Software-Circuit-Device Co-Optimization Framework for Neuromorphic Inference Circuits,” IEEE Access, Vol. 10, pp. 41078-41086, 2022.
[5]P.D. Schiavone, D. Rossi, A. Di Mauro, F.K. Gürkaynak, T. Saxe, M. Wang, K.C. Yap, and L. Benini, “Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 29, No. 4, pp. 677-690, 2021.
[6]M. Zanghieri, P.M. Rapa, M. Orlandi, E. Donati, L. Benini, and S. Benatti, “Event-based Estimation of Hand Forces from High-Density Surface EMG on a Parallel Ultra-Low-Power Microcontroller,” IEEE Sensors Journal, 2024.
[7]J. Végh and Á.J. Berki, “On the role of speed in technological and biological information transfer for computations,” Acta Biotheoretica, Vol. 70, No. 4, pp. 26, 2022.
[8]R.A. Khalil, N. Saeed, M. Masood, Y.M. Fard, M.S. Alouini and T.Y. Al-Naffouri, “Deep learning in the industrial internet of things: Potentials, challenges, and emerging applications,” IEEE Internet of Things Journal, Vol. 8, No. 14, pp. 11016-11040, 2021.
[9]W. Guo, H.E. Yantır, M.E. Fouda, A.M. Eltawil and K.N. Salama, “Towards efficient neuromorphic hardware: unsupervised adaptive neuron pruning,” Electronics, Vol. 9, No. 7, pp. 1059, 2020.
[10]T. Jia, Y. Ju, R. Joseph and J. Gu, “Ncpu: An embedded neural cpu architecture on resource-constrained low power devices for real-time end-to-end performance,” In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2020, October), pp. 1097-1109. IEEE.
[11]A. Katal, S. Dahiya and T. Choudhury, “Energy efficiency in cloud computing data centers: a survey on software technologies,” Cluster Computing, Vol. 26, No. 3, pp. 1845-1875, 2023.
[12]S. Bian, L. Schulthess, G. Rutishauser, A. Di Mauro, L. Benini, and M. Magno, “Colibriuav: An ultra-fast, energy-efficient neuromorphic edge processing uav-platform with event-based and frame-based cameras,” In 2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI), pp. 287-292. IEEE.
[13]B. Rana, Y. Singh and P.K. Singh, “A systematic survey on internet of things: Energy efficiency and interoperability perspective,” Transactions on Emerging Telecommunications Technologies, Vol. 32, No. 8, pp. e4166, 2023, June.
[14]T. Wan, S. Ma, F. Liao, L. Fan and Y. Chai, “Neuromorphic sensory computing,” Science China Information Sciences, Vol. 65, pp. 1-14, 2022.
[15]S. Bian, E. Donati, and M. Magno, “Evaluation of Encoding Schemes on Ubiquitous Sensor Signal for Spiking Neural Network, “ IEEE Sensors Journal, 2024.
[16]B. Nie, S. Liu, Q. Qu, Y. Zhang, M. Zhao, and J. Liu, “Bio-inspired flexible electronics for smart E-skin,” Acta Biomaterialia, Vol. 139, pp. 280-295, 2022.
[17]A. Garofalo, G. Tagliavini, F. Conti, L. Benini, and D. Rossi, “Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes,” IEEE Transactions on Emerging Topics in Computing, Vol. 9, No. 3,  pp. 1489-1505, 2021.
[18]S. Shukla, and K.C. Ray, “A low-overhead reconfigurable RISC-V quad-core processor architecture for fault-tolerant applications,” IEEE Access, Vol. 10, pp. 44136-44146, 2022.
[19]A. Kamaleldin and D. Göhringer, “Agiler: An adaptive heterogeneous tile-based many-core architecture for risc-v processors,” IEEE Access, Vol. 10, pp. 43895-43913, 2022.
[20]A. Coluccio, A. Ieva, F. Riente, M.R. Roch, M. Ottavi, and M. Vacca, “RISC-Vlim, a RISC-V framework for logic-in-memory architectures,” Electronics, Vol. 11, No. 19, pp. 2990, 2022.
[21]Z. Dong, X. Ji, G. Zhou, M. Gao and D. Qi, “Multimodal neuromorphic sensory-processing system with memristor circuits for smart home applications,” IEEE Transactions on Industry Applications, Vol. 59, No. 1, pp. 47-58, 2022.
[22]S. Nazari, A. Keyanfar and M.M. Van Hulle, “Neuromorphic circuit based on the un-supervised learning of biologically inspired spiking neural network for pattern recognition,” Engineering Applications of Artificial Intelligence, Vol. 116, pp. 105430, 2022.
[23]C. Gillet, A. F. Vincent, B. Le Gal and S. Saïghi, “A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding,” IEEE Access, 2023.
[24]G. Rutishauser, R. Hunziker, A. Di Mauro, S. Bian, L. Benini, M. Magno, “Colibries: A milliwatts risc-v based embedded system leveraging neuromorphic and neural networks hardware accelerators for low-latency closed-loop control applications,” In 2023 IEEE International Symposium on Circuits and Systems (ISCAS), (2023, May), pp. 1-5. IEEE.
[25]P.D. Schiavone, D. Rossi, A. Di Mauro, F.K. Gürkaynak, T. Saxe, M. Wang, K.C. Yap, and L. Benini, “Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 29, No. 4, pp. 677-690, 2021.
[26]E. Hassan, Z. Zou, H. Chen, M. Imani, Y. Zweiri, H. Saleh, and B. Mohammad, “Efficient event-based robotic grasping perception using hyperdimensional computing,” Internet of Things, Vol. 26, pp. 101207, 2024.
[27]G. Leone, M.A. Scrugli, L. Badas, L. Martis, L. Raffo, and P. Meloni, “A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
[28]J. C. Isaksen, “Design And Test Of A Neural Microprocessor,” 2022.
[29]P.V. Bindu and J. Afthab, “Region of interest based medical image compression using DCT and capsule autoencoder for telemedicine applications,” In 2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT) 2021, September; 1-7. IEEE.
[30]X. Pei, Y. hong Zhao, L. Chen, Q. Guo, Z. Duan, Y. Pan, and H. Hou, “Robustness of machine learning to color, size change, normalization, and image enhancement on micrograph datasets with large sample differences,” Materials & Design, Vol. 232, pp. 112086, 2023.
[31]D. Auge, J. Hille, E. Mueller and A. Knoll, “A survey of encoding techniques for signal processing in spiking neural networks,” Neural Processing Letters, Vol. 53, No. 6,  pp. 4693-4710, 2021. 
[32]L. Zanatta, A. Di Mauro, F. Barchi, A. Bartolini, L. Benini and A. Acquaviva, “Directly-trained Spiking Neural Networks for Deep Reinforcement Learning: Energy efficient implementation of event-based obstacle avoidance on a neuromorphic accelerator,” Neurocomputing, Vol. 562, pp. 126885, 2023.
[33]N. Frías, F. Johnson, and C. Valle, “Hybrid Algorithms for energy minimizing vehicle routing problem: integrating clusterization and ant colony optimization,” IEEE Access 2023.
[34]S.Y. Lee, Y.W. Hung, Y.T. Chang, C.C. Lin and G.S. Shieh, “RISC-V CNN coprocessor for real-time epilepsy detection in wearable application,” IEEE transactions on biomedical circuits and systems, Vol. 15, No. 4, pp. 679-691, 2021.
[35]Smith, O.J.M. and Kantor, K.N., 2024, June. Design and evaluation of neuromorphic hardware architectures for low-power edge AI applications. In ECCSUBMIT Conferences, Vol. 2, No. 2, pp. 51-57.
[36]Wang, J., Wu, R., Chen, G., Chen, X., Liu, B., Zong, J. and Zhao, D., 2022. RISC-V toolchain and agile development based open-source neuromorphic processor. arXiv preprint arXiv:2210.00562.