International Journal of Computer Network and Information Security(IJCNIS)

ISSN: 2074-9090 (Print), ISSN: 2074-9104 (Online)

Published By: MECS Press

IJCNIS Vol.14, No.4, Aug. 2022

Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip

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Sangeeta Singh, J V R Ravindra, B. Rajendra Naik

Index Terms

Network on Chip (NoC);Intermittent Failure;Crosstalk Noise;Power gating


With the emergence of deep sub-micron technology, the reliability issues in on-chip interconnect has enormously increased. This includes single event upsets, like soft errors, and hard faults which are rapidly becoming important factors to be considered. Aggressive technology scaling renders these architectures vulnerable to system performance, intermittent failure, capacitive crosstalk, and power dissipation problem. To improve the performance of the area and power consumption along with bandwidth, throughput and latency, a Buffer Potency Power Gating Technique is carried out to predict the Intermittent Failure by Presage Debacle Model in Network on Chip. In the Presage Debacle Model, the links present in the application-specific topology are provided with real application traffic to assist in prediction of the intermittent failure. By predicting the failure, the output of the model provides the power dissipated over the connection of the application link. Then the crosstalk noise in the topology is reduced by the Adaption of Simulated Annealing (SA) based Particle Swarm Optimization (PSO) congruence algorithm. The optimization congruence algorithm assigns each task in the application software to each node in the topology to determine the network's optimal output. It continuously changes the task park position in the topology system and reduces the crosstalk of the NoC. Consecutively, the area and power consumption are minimized by Buffer Potency Power Gating Technique. Buffer efficiency is increased and the power-gating is a practical way to mitigate NoC power control schemes properly and effectively without any loss in performance. Thus the prediction of intermittent failure is obtained by utilizing NoC to improve the performance of area and power consumption.

Cite This Paper

Sangeeta Singh, J V R Ravindra, B. Rajendra Naik, "Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip", International Journal of Computer Network and Information Security(IJCNIS), Vol.14, No.4, pp.75-88, 2022. DOI:10.5815/ijcnis.2022.04.06


[1]N. L. Venkataraman, and R. Kumar, “Design and analysis of application-specific network on chip for reliable custom topology,” Computer Networks, vol. 158, pp. 69-76, 2019.

[2]Sangeeta Singh, et. al., “Power and Area Calibration of Switch Arbiter for High Speed Switch Control and Scheduling in Network-on-Chip,” In IEEE 13th International SoC Design Conference (ISOCC), pp. 5-6, 2016.

[3]S. Paul, N. Chatterjee, and P. Ghosal, “A permanent fault-tolerant dynamic task allocation approach for Network-on-Chip based multicore systems,” Journal of Systems Architecture, vol. 97, pp. 287-303, 2019.

[4]R. Poovendran, and S. Sumathi, “An area‐efficient low‐power SCM topology for high-performance network‐on Chip (NoC) architecture using an optimized routing design,” Concurrency and Computation: Practice and Experience, vol. 31, no. 14, pp. e4760, 2019.

[5]P. Kullu, and S. Tosun, “Energy-aware and fault-tolerant custom topology design method for network-on-chips,” Nano Communication Networks, vol. 19, pp. 54-66, 2019.

[6]C. L. Li, J. C. Yoo, and T. H. Han, “Energy-efficient custom topology-based dynamic voltage-frequency island-enabled network-on-chip design,” Journal Of Semiconductor Technology And Science, vol. 18, no. 3, pp. 352-359, 2018.

[7]C. H. U. Zhuqin, L. I. Hui, G. U. Huaxi, and Y.E. Xiaochun, “Wavelength assignment method based on ACO to reduce crosstalk for ring-based optical network-on-chip,” Microprocessors and Microsystems, vol. 71, pp. 102849, 2019.

[8]B. Subramaniam, S. Muthusamy, and G. Gengavel, “Crosstalk minimization in the network on chip (NoC) links with dual binary-weighted code CODEC,” Journal of Ambient Intelligence and Humanized Computing, pp. 1-6, 2020.

[9]A. Jedidi, “Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip,” International Journal of Electrical and Computer Engineering, vol. 8, no. 6, pp. 4912, 2018.

[10]H. A. M. Harb, et al., “A Study of the Number of Wavelengths Impact in the Optical Burst Switching Core Node,” Proceeding of the Electrical Engineering Computer Science and Informatics, pp. 664-667, 2017.

[11]L. H. Duong, P. Yang, Z. Wang, Y. S. Chang, J. Xu, Z. Wang, and X. Chen, “Crosstalk noise reduction through adaptive power control in inter/intra-chip optical networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 1, pp. 43-56, 2018.

[12]N. Chatterjee, P. Mukherjee, and S. Chattopadhyay, “Reliability-aware application mapping onto mesh-based Network-on-Chip,” Integration, vol. 62, pp. 92-113, 2018.

[13]N. K. R. Beechu, V. M. Harishchandra, and N. K. Y. Balachandra, “Energy-aware and reliability-aware mapping for NoC-based architectures,” Wireless Personal Communications, vol. 100, no. 2, pp. 213-225, 2018.

[14]W. Gao, Z. Qian, and P. Zhou, “Reliability-and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation,” Integration, vol. 65, pp. 351-361, 2019.

[15]M. G. Moghaddam, and C. Ababei, “Dynamic lifetime reliability management for chip multiprocessors,” IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 4, pp. 952-958, 2018.

[16]L. Daoud, and N. Rafla, “Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip,” In 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp. 266-271, 2019. 

[17]B. Bhowmik, S. Biswas, J. K. Deka, and B. B. Bhattacharya, “Reliability-aware test methodology for detecting short-channel faults in on-chip networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 6, pp. 1026-1039, 2018.

[18]A. Rodríguez-Ramos, A. J. da Silva Neto, and O. Llanes-Santiago, “An approach to fault diagnosis with online detection of novel faults using fuzzy clustering tools,” Expert Systems with Applications, vol. 113, pp. 200-212, 2018.

[19]M. H. Moaiyeri, F. Sabetzadeh, and S. Angizi, “An efficient majority-based compressor for approximate computing in the nano era,” Microsystem Technologies, vol. 24, no. 3, pp. 1589-1601, 2018.

[20]S. Velayudham, S. Rajagopal, Y. V. R. Rao, and S. B. Ko, “Power-efficient error correction coding for on-chip interconnection links,” IET Computers & Digital Techniques, vol. 14, no. 6, pp. 299-312, 2020.

[21]M. Vinodhini, N. S. Murty and T. K. Ramesh, “Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC,” IEEE Access, vol. 8, pp. 174614-174628, 2020.

[22]A. K. Chlaab, W. N. Flayyih, and F. Z. Rokhani, “Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on-chip interconnects,” Bulletin of Electrical Engineering and Informatics, vol.  9, no. 5, pp. 1979-1989, 2020.

[23]M. Vinodhini, and N. S. Murty, “Reliable low power NoCinterconnects,” Microprocessors and Microsystems, vol. 57, pp. 15-22, 2018.

[24]Javed, Aqib, et al. "Exploring spiking neural networks for prediction of traffic congestion in networks-on-chip." 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020.

[25]Wang, Ke, and Ahmed Louri. "Cure: A high-performance, low-power, and reliable network-on-chip design using reinforcement learning." IEEE Transactions on Parallel and Distributed Systems 31.9 (2020): 2125-2138.

[26]Amin, W., Hussain, F., Anjum, S., Khan, S., Baloch, N.K., Nain, Z. and Kim, S.W., 2020. Performance evaluation of application mapping approaches for network-on-chip designs. IEEE Access, 8, pp.63607-63631.

[27]Bhanu, P. Veda, and J. Soumya. "Fault-tolerant application mapping on mesh-of-tree based network-on-chip." Journal of Systems Architecture 116 (2021): 102026.