International Journal of Information Technology and Computer Science(IJITCS)

ISSN: 2074-9007 (Print), ISSN: 2074-9015 (Online)

Published By: MECS Press

IJITCS Vol.5, No.11, Oct. 2013

Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic

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Abdul Sajid, Ahmad Nafees, Saifur Rahman

Index Terms

Adiabatic Logic, GATE, Power Analysis, CMOS


Addition forms the basic structure for many processing operations like counting, multiplication, filtering etc. Adder circuits that add two binary numbers are of great interest for many designers. The simplest approach to design an adder is to implement gates to yield the required logic function. Carry-look ahead adder is a major functional block in arithmetic logic unit due to its high speed operation. The arithmetic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. Therefore, it is of interest to study the functional behavior and power consumption carry-look ahead adder. In this project, the adder is implemented using 180 nm CMOS technology on bulk substrate. Two logic families i.e. static CMOS and adiabatic logic have been analyzed and implemented to study the transient characteristics of the adder. Finally the power consumption is estimated and compared. From the results it has been found that the static CMOS logic offers low delay whereas the adiabatic logic consumes low power.

Cite This Paper

Abdul Sajid, Ahmad Nafees, Saifur Rahman,"Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic", International Journal of Information Technology and Computer Science(IJITCS), vol.5, no.11, pp.78-92, 2013. DOI: 10.5815/ijitcs.2013.11.09


[1]M. I. Elmasry, “Digital MOS integrated circuits: A tutorial;’ Digital MOS Integrated Circuits. New York: IEEE Press pp. 4-27.

[2]A. Kapuma,” CMOS circuit optimization,” Solid-State Electronics, vol. 26, no. 1, pp: 47-58, 1983.

[3]C. Mead and L. Conway, Introduction to VLSI Systems. New York: pp. 12-15.

[4]I. S. Abu-Khater, R H Yan, A. Bellaouar and M. I. Elmayry, “A 1- V low-power high-performance 32-bit conditional sum adder,” in 19% IEEE Symposium on Low Power Electronics, Oct 10-12, 1994, San Diego. pp 66-67.

[5]I. S. Abu-Khater, A Bellaouar, M. I. Elmasry, and R Yan, “Circuit/architecture for low-power high-perrormance 32bit adder.” in IEEE sponsored 5th Great Lakes VLSI Symposium, Buffalo, New York, March 1995, pp. 74-77. 

[6]K. Yano, et al., “A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic,” IEEE Journal of Solid State Circuits, vol. 25, no. 2, pp. 388-395, April 1990. 

[7]J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 2nd ed., 2003. 

[8] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEE Proceedings: Circuits, Devices and Systems, vol. 148, no. 1, pp. 19-24, Feb. 2001. 

[9]S. Goel, A. Kumar, and M. A. Bayoumi, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309-1321, Dec. 2006. 

[10]R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of SolidState Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997. 

[11]M. Alioto and G. Palumbo, “Analysis and comparison on full adder block in submicron technology,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 806-823, Dec. 2002.

[12]Guoqiang Hang, “Adiabatic CMOS Gate and Adiabatic Circuit Design for Low-Power Applications,” Design Automation Conference, 2005, pp. 803-808.

[13]W.C. Athas and L.J. Svensson, “Reversible Logic Issues in Adiabatic CMOS,” Physics and Computation, 1994, Proceedings, pp. 111-118.

[14]Dragan Maksimovic, Vojin G. Oklobdiija, Borivoje Nikolic, K. Wayne Current, “Clocked CMOS Adiabatic Logic with Integrated Single-phase Power-Clock Supply: Experimental Results,” Low Power Electronics and Design, 1997, pp. 323 – 327.

[15]Jose C. Garcia, and Juan A. Montiel–Nelson and Saeid Nooshabadi, “A CMOS Adiabatic Inverter Operating with a Single Clock Power Supply to Reduce Non–Adiabatic Loss,” IEEE Asia Pacific conference on Circuits and Systems, APCCAS 2008, pp. 968 – 971.

[16]Dragan Maksimovic´, Vojin G. Oklobdžija, Borivoje Nikolic, and K. Wayne Current, “Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply,” SoC Design Conference, 2008, pp. 350-353.

[17]Ettore Amirante , Jiirgen Fischer, M a r h s Lang , Agnese Bargagli-Stoffi , Jorg Berthold, Christoph Heer, and Dons Schmitt-Landsiedel, “An Ultra Low-Power Adiabatic Adder Embedded in a Standard 0.13pm CMOS Environment,” Solid-State Circuits Conference, 2003, pp. 599 - 602.

[18]Hee-sup Song and Jin-ku Kang, “A CMOS Adiabatic Logic for Low Power Circuit Design,” 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004, pp. 348-351.

[19]Nazrul Anuar, Yasuhiro Takahashi and Toshikazu Sekine, “Two Phase Clocked Adiabatic Static CMOS Logic,” International symposium on System-on-Chip, 2009, pp. 83-86.