Design of Low Power Sequential Circuit by using Adiabatic Techniques

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Priyanka Ojha 1,* Charu Rana 1

1. ITM University/Department of EECE, Gurgaon, 122001, India

* Corresponding author.


Received: 20 Nov. 2014 / Revised: 12 Feb. 2015 / Accepted: 11 Apr. 2015 / Published: 8 Jul. 2015

Index Terms

Adiabatic Switching, Energy Dissipation, AC Power Supply, Inverter, D Latch And D Flip-Flop


Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.

Cite This Paper

Priyanka Ojha, Charu Rana, "Design of Low Power Sequential Circuit by using Adiabatic Techniques", International Journal of Intelligent Systems and Applications(IJISA), vol.7, no.8, pp.45-50, 2015. DOI:10.5815/ijisa.2015.08.06


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