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Area-power-temperature trade-off, Mixed Polarity Reed-Muller, Polarity conversion, Genetic Algorithm, VLSI, HotSpot
Modern Integrated circuits (ICs) suffer from excessive power and temperature issues because of embedding a large number of applications on small silicon real estate. Low power technique is introduced to reduce the power. With the reduction of power, area of circuit increases and vice versa. It shows a trade-off nature between them. Increase of area is against the trend of technology scaling which demands small area. Due to small area and high power dissipation, power-density increases. As power-density is directly converging into temperature, it emerges as a challenge in front of the VLSI design engineer to minimize the effect of temperature by reducing power-density. In this work, an attempt has been made to reduce the effect of power-density along with area and power so that AND-XOR based circuit is balanced in terms of area, power, and temperature. AND-XOR based reed-muller (RM) mixed polarity circuit forms are considered in this work. Polarity conversions are made in such a way that possibility of maximum sharing among the sub-function is increased. Genetic algorithm is (a non-exhaustive heuristic algorithm) used to select the polarity of the input variable for maximum sharing. The proposed synthesis approach shows 27.11%, 20.69%, and 32.30% savings in area, power, and power-density respectively than that of reported results. For the validation of the proposed approach, the best solutions are implemented in Cadence digital domain to obtain actual silicon area and power consumption. HotSpot tool is used to get the absolute temperature of the circuit.
Apangshu Das, Sambhu Nath Pradhan, "Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion", International Journal of Intelligent Systems and Applications(IJISA), Vol.10, No.12, pp.35-46, 2018. DOI:10.5815/ijisa.2018.12.04
J. Saul, “Logic Synthesis for Arithmetic Circuits using the Reed-Muller Representation”, IEEE Proceedings of 3rd European Conference on Design Automation. March, 1992. 109-113. doi: 10.1109/EDAC.1992.205904.
L. Wang, “Automated Synthesis and Optimization of Multilevel Logic Circuits”, Doctoral dissertation, Napier University, 2000.
T. Sasao, “Switching Theory for Logic Synthesis”, Springer Science & Business Media, 2012.
W. Pengjun and L. Hui, “Low Power Mapping for AND/XOR Circuits and its Application in Searching the Best Mixed-Polarity”, Journal of Semiconductors, Vol. 32, no.2, 025007, 2011.
H. Rahaman, D. K. Das and B. B. Bhattacharya, “Testable Design of AND–EXOR Logic Networks with Universal Test Sets”, Computers & Electrical Engineering, Vol. 35, no. 5, pp. 644-658, 2009. doi: https://doi.org/10.1016/j.compeleceng.2009.01.006.
S. B. Ko and J. C. Lo. "Efficient Realization of Parity Prediction Functions in FPGAs", Journal of Electronic Testing, Vol. 20, no. 5, pp. 489-499, 2004. doi: 10.1023/B:JETT.0000042513.15382.e7.
S. N. Pradhan and S. Chattopadhyay. “Two-level AND XOR Networks Synthesis with Area-Power Trade-off”, Int. J. Comput. Sci. Network Security, vol. 8, no. 9, pp. 365-375, 2008.
S. Chattopadhyay, S. Roy, and P. P. Chaudhuri. “Synthesis of Highly Testable Fixed Polarity AND-XOR Canonical Networks - a Genetic Algorithm Based Approach”, IEEE Trans. on Computers, vol. 45, no. 4, pp. 487-490, April 1996. doi: 10.1109/12.494107.
T. Sasao and P. Besslich. “On the Complexity of Mod-2-Sum PLAs”, IEEE Trans.on Computers, vol. 39, no. 2, pp. 262-266, February, 1990. doi: 10.1109/12.45212.
M. A. Perkowski, L. Csanky, A. Sarabi and I. Schafer. "Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks", Computer Design: VLSI in Computers and Processors, 1992. ICCD'92. Proceedings, IEEE 1992 International Conference on. IEEE, 1992, pp. 33-36. doi: 10.1109/ICCD.1992.276211.
T. Sasao. “EXMIN2: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple Valued Input Two-Valued Output Functions”, IEEE Transaction on CAD, vol. 12, no. 5, pp. 621-632, May, 1993. doi: 10.1109/43.277608.
H. Li, P. Wang and J. Dai, "Area Minimization of MPRM Circuits", ASICON'09. 8th IEEE International Conference on ASIC. pp. 521-524, 2009. doi: 10.1109/ASICON.2009.5351633.
I. Reed. “A Class of Multiple-Error-Correcting Codes and the Decoding Scheme”, Transactions of the IRE Professional Group on Information Theory, Vol. 4, no. 4, pp. 38-49, 1954. doi: 10.1109/TIT.1954.1057465.
M. Davio, Y. Deschamps and A. Thayse. Discrete and switching Functions. George and McGraw-Hill, NY, 1978.
H. Wu, M. A. Perkowski, X. Zeng, and N. Zhuang. "Generalized Partially-Mixed-Polarity Reed-Muller Expansion and its Fast Computation", IEEE transactions on computers Vol. 45, no. 9, pp. 1084-1088, 1996. doi: 10.1109/12.537134.
M. Yang, H. Xu, and A. E. A. Almaini. "Optimization of Mixed Polarity Reed-Muller Functions Using Genetic Algorithm", Computer Research and Development (ICCRD), 2011 3rd International Conference on. Vol. 3. IEEE, 2011. doi: 10.1109/ICCRD.2011.5764198.
Al Jassani, B. A., N. Urquhart, and A. E. A. Almaini. "Manipulation and Optimisation Techniques for Boolean Logic", IET Computers & Digital Techniques, Vol. 4, no. 3, pp. 227-239, 2010. doi: 10.1049/iet-cdt.2009.0007.
L. Xiao, et.al., “Optimization of Best Polarity Searching for Mixed Polarity Reed-Muller Logic Circuit”, 28th IEEE International Conference on System-on-Chip (SOCC), 2015, pp. 275-280.
He, Zhenxue, et.al., "An Efficient and Fast Polarity Optimization Approach for Mixed Polarity Reed-Muller Logic Circuits", Frontiers of Computer Science, Vol. 11, no. 4, pp. 728-742, 2017.
Y. Ye and K. Roy. "A Graph-Based Synthesis Algorithm for AND/XOR Networks", Proceedings of the 34th Design Automation Conference, Anaheim, CA, USA, 1997, pp.107-112. doi: 10.1109/DAC.1997.597126.
He. Zhen-Xue, et al., "A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions", Journal of Computer Science and Technology, Vol. 32, no. 2, pp. 297-311, 2017. doi: DOI 10.1007/s11390-017-1723-1.
X. Wang, et al., "Power Optimization in Logic Synthesis for Mixed Polarity Reed-Muller Logic Circuits", The Computer Journal, Vol. 58, no. 6, pp. 1306-1313, 2015.
S. Chaudhury, and S. Chattopadhyay, "Fixed polarity Reed-Muller Network Synthesis and its Application in AND-OR/XOR-Based Circuit Realization with Area-Power trade-off", IETE Journal of Research, Vol. 54, no. 5, pp. 353-363, 2008. Doi: http://dx.doi.org/10.4103/0377-2063.48540.
S. Gunther, F. Binns, D. M. Carmean, and J. C. Hall, “Managing the Impact of Increasing Microprocessor Power Consumption”, Intel Technology Journal, vol. 5, no. 1, pp. 1-9, 2001.
A. Das, and S. N. Pradhan, “Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits”, VLSI Design, Vol. 2016, pp. 1-14, 2016. doi: http://dx.doi.org/10.1155/2016/3191286.
A. Das and S. N. Pradhan, "Thermal Aware FPRM Based AND-XOR Network Synthesis of Logic Circuits," 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS), Kolkata, 2015, pp. 497-502. doi: 10.1109/ReTIS.2015.7232930.
A. Das and S. N. Pradhan, "Thermal aware Output Polarity Selection of Programmable Logic Arrays", International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), Shillong, 2015, pp.68-71. doi: 10.1109/EDCAV.2015.7060541.
M. Pedram and S. Nazarian, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods", in Proceedings of the IEEE, vol. 94 (8), pp. 1487-1501, Aug. 2006. doi: 10.1109/JPROC.2006.879797.
M. Davio, Y. Deschamps, and A. Thayse, “Discrete and switching Functions”, George and McGraw-Hill, NY, 1978.
C.K. Vijayakumari, P. Mythili, K. J. Rekha,"A Simplified Efficient Technique for the Design of Combinational Logic Circuits", International Journal of Intelligent Systems and Applications (IJISA), vol.7, no.9, pp.42-48, 2015. DOI: 10.5815/ijisa.2015.09.06.
S. Goyal, J. Singh, "Two-Level Alloyed Branch Predictor based on Genetic Algorithm for Deep Pipelining Processors", International Journal of Modern Education and Computer Science(IJMECS), Vol.9, No.5, pp. 27-33, 2017.DOI: 10.5815/ijmecs.2017.05.04.
H. M. Mousa, "DNA-Genetic Encryption Technique", International Journal of Computer Network and Information Security(IJCNIS), Vol. 8, No. 7, pp. 1-9, 2016. DOI: 10.5815/ijcnis.2016.07.01.
A. Chandel, M. Sood, "A Genetic Approach Based Solution for Seat Allocation during Counseling for Engineering Courses", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol. 8. No. 1, pp. 29-36, 2016. DOI: 10.5815/ijieeb.2016.01.04.
A. Das, S. R. Choudhury, B. K. Kumar and S. N. Pradhan, "An Elitist Area-Power Density Trade-off in VLSI Floorplan Using Genetic Algorithm", 7th International Conference on Electrical and Computer Engineering, Dhaka, 2012, pp. 729-732. doi: 10.1109/ICECE.2012.6471654.
HotSpot tool available on: http://lava.cs.virginia.edu/HotSpot/download_form2.html. Accessed: 3rd of July 2017.