Memory Controller and Its Interface using AMBA 2.0

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Hitanshu Saluja 1 Naresh Grover 1

1. Department of Electronics & Communication, Manav Rachna International Institute of Research and Studies, Faridabaad, Hrayana, India

* Corresponding author.


Received: 15 Jan. 2019 / Revised: 21 Mar. 2019 / Accepted: 25 Apr. 2019 / Published: 8 Jul. 2019

Index Terms

AMBA, AHB Master, AHB Slave, SOC, Xilinx


This paper elaborates the AMBA bus interface bridge between memory controller and other supporting peripheral. The work claims the integration with FIFO, RAM and ROM with slave interface and the master of AHB bus. The AHB master initiates the operation and generates the necessary control signal. Memory controller is implemented with finite state machine considering with all the peripheral works in synchronous mode. Despite these shortcomings of the work performed study and development that followed has led the development of a memory controller on AMBA-AHB bus at a very advanced stage and next to prototyping. VHDL code is utilized to develop the design and it is synthesized in Xilinx Virtex 6 device (XC6VCX75T). The design claims a minor area overhead with improvement in speed 185.134 MHz.

Cite This Paper

Hitanshu Saluja, Naresh Grover," Memory Controller and Its Interface using AMBA 2.0", International Journal of Engineering and Manufacturing(IJEM), Vol.9, No.4, pp.33-44, 2019. DOI: 10.5815/ijem.2019.04.03


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