International Journal of Engineering and Manufacturing (IJEM)
IJEM Vol. 16, No. 4, 8 Aug. 2026
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Design and Implementation of a 16-Bit ALU Using Structural Verilog
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Author(s)
Index Terms
Arithmetic Logic Unit, Structural Verilog, Ripple Carry Adder, Bit-Sliced Architecture, 2’s Complement, Digital Logic Design, and Propagation Delay
Abstract
The Arithmetic Logic Unit (ALU) is a fundamental building block of all modern central processing units (CPUs). This papers presents the design and implementation of a 16-bit, 4-function ALU constructed entirely from basic logic gates, using a structural Verilog approach. The ALU supports four operations: addition, subtraction, bitwise AND, and bitwise OR, implemented via a modular, bit-sliced architecture. A single ripple-carry adder with 2's complement logic performs both arithmetic operations efficiently. Operation selection is achieved through a 2-bit control signal and a 4-to-1 multiplexer per bit slice. The system was verified using QuestaSim simulation with both normal and boundary test vectors. Unlike existing behavioral or high-level implementations, this work contributes a fully gate-level structural model that makes every interconnection explicit, enabling transparent analysis of carry propagation and delay. Performance metrics including propagation delay and hardware resource usage are analyzed. The results validate the design's functional correctness and demonstrate its potential as a scalable building block for processor architectures.
Cite This Paper
Punith Kumar M. B., Yashaswini H. A., "Design and Implementation of a 16-Bit ALU Using Structural Verilog", International Journal of Engineering and Manufacturing (IJEM), Vol.16, No.4, pp.253-262, 2026. DOI:10.5815/ijem.2026.04.17
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