Power-Time Efficient Hybrid Adder Design Based on LP with Optimal Bit-Width Generation

Full Text (PDF, 831KB), PP.1-12

Views: 0 Downloads: 0


Mahmoud A. M. Alshewimy 1,*

1. Computer and Control Engineering Department, Tanta University, Egypt

* Corresponding author.

DOI: https://doi.org/10.5815/ijem.2020.04.01

Received: 8 Jan. 2020 / Revised: 20 Jan. 2020 / Accepted: 28 Jan. 2020 / Published: 8 Aug. 2020

Index Terms

Delay, hybrid adder, linear programming, optimal, power.


This paper presents a systematic method for a hybrid adder design through allocating the optimal bit-widths and types of classical adders constituting a hybrid adder. The proposed optimization scheme considers two aspects design delay and power. It is based on a mathematical modeling of the proposed hybrid adder architecture following the principle of LP (Linear Programming). Two models, delay optimization under power constraint and power optimization under delay constraint, are introduced. Various experiments are presented to demonstrate the effectiveness and applicability of the proposed design scheme. The results indicate that the proposed scheme successfully allocates simultaneously and in a systematic way the optimal bit-widths of the sub-adders constituting a hybrid adder; providing an improvement in (power x delay)  performance reaching 71.6%. The results obtained also indicate that the proposed design scheme introduces a high flexibility in making a compromise between delay and power of the adder design.

Cite This Paper

Mahmoud A. M. Alshewimy, " Power-Time Efficient Hybrid Adder Design Based On Lp With Optimal Bit-Width Generation ", International Journal of Engineering and Manufacturing (IJEM), Vol.10, No.4, pp.1-12, 2020. DOI: 10.5815/ijcnis.2020.04.01


[1]Hennessy, J.L & Patterson, D.A. (1990). Computer Architecture: A Quantitative Approach.  Morgan Kaufmann.  

[2]Franklin, M.A. & Pan, T. (1994). Performance Comparison of Asynchronous Adders. In: Symp. on Advanced Research in Asynchronous Circuits and Systems, pp. 117-125. 

[3]Garside, J.D. (1993). CMOS VLSI Implementation of an Asynchronous ALU. In: Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, pp. 181-192.

[4]Koren, I. (2002). Computer Arithmetic Algorithms, (2nd ed.), A K Peters Ltd., Canada. 

[5]Lynch, T. & Swartzlander, E. E. (1993). A spanning Tree Carry Look-ahead Adder. IEEE Trans.on Computers, 41 (August 1992), 931-939.

[6]Wang, Y., Pai, C., & Song, X. (2002). Design of Hybrid Carry Look-ahead/Carry–Select Adders. IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 1.

[7]Li, J., Yu, J., & Huang, Y. (2005). A Design Methodology for Hybrid Carry Look-ahead/Carry-Select Adders with Re-configurability. In: Proc. 15th VLSI/CAD Symp., Pintung.

[8]Lakshmanan, Meaamar, A., & Othman, M. (2006). High-Speed Hybrid Parallel-Prefix Carry- Select Adder Using Ling's Algorithm. In: ICSE2006 Proc., Kuala Lumpur, Malaysia.

[9]Nithya, J. & Ramesh, S. R., (2019). Design of Delay Efficient Hybrid Adder for High Speed Applications. 5th International Conference on Advanced Computing & Communication Systems (ICACCS), Coimbatore, India, 2019, pp. 374-378.

[10]Joel, A., & Manjith, R. (2019). Design of Low Power High Speed Hybrid Adder Using Gdi Technique. International Journal of Advance and Innovative ResearchVolume 6, Issue 1.

[11]Zimmermann, R. (1997). Binary Adder Architectures for Cell – Based VLSI and their Synthesis, Ph.D., Swiss Federal Institute of Technology, Zurich. 

[12]Weinberger, & Smith, J. L. (1958). Logic for High- Speed Addition, National Bureau of 

[13]Standards, Circulation 591, pp. 3-1. Kilburn, T., Edwards, D.B.G., & Aspinall, D. (1959). Parallel Addition in Digital Computers:  A New Fast "Carry” Circuit. In: IEE, Vol.106, Pt.B. pp.464.

[14]Sklansky, J. (1960). Conditional Sum Addition Logic. IRE Trans. Electron. Comput., vol.  EC-9, no. 6, pp. 226–231.

[15]Brent, R.P., & Kung, H.T. (1982). Regular Layout for Parallel Adders. In: IEEE Trans.  Comput., vol.31, no. 3, pp. 260–264.

[16]Vanderbei, R.J. (2001). Linear Programming: Foundations and Extensions. (2nd ed.), USA.